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static inline void core_sleep(unsigned int core){#ifdef CPU_PP502x    /* This will sleep the core if no wake was requested */    asm volatile (        "mrs    r2, cpsr             \r\n" /* disable interrupts for timely execution */        "orr    r2, r2, #0xc0        \r\n"        "msr    cpsr_c, r2           \r\n"        "mov    r1, #0x80000000      \r\n"        /* */        "ldr    r0, [%1, %2, lsl #2] \r\n" /* check mailbox */        "nop                         \r\n"        "cmp    r0, #0               \r\n" /* wake requested? */        "streq  r1, [%0, %2, lsl #2] \r\n" /* sleep if not */        "nop                         \r\n"        "mov    r0, #0               \r\n"        "str    r0, [%0, %2, lsl #2] \r\n" /* clear control reg */        /* */        "bic    r2, r2, #0xc0        \r\n" /* reenable interrupts */        "msr    cpsr_c, r2           \r\n"        :        : "r"(&CORE_CTL(CPU)), "r"(&CORE_MESSAGE(CPU)), "r" (core)        : "r0", "r1", "r2");#else    CORE_CTL(core) = PROC_SLEEP;#endif}void core_wake(unsigned int othercore){#ifdef CPU_PP502x    /* avoid r0 since that contains othercore */    asm volatile (        "mrs    r2, cpsr             \r\n" /* disable interrupts for timely execution */        "orr    r3, r2, #0xc0        \r\n"        "msr    cpsr_c, r3           \r\n"        "mov    r1, #1               \r\n"        /* */        "str    r1, [%1, %2, lsl #2] \r\n"        "nop                         \r\n"        "nop                         \r\n"        "ldr    r1, [%0, %2, lsl #2] \r\n"        "tst    r1, #0x80000000      \r\n"        "bic    r1, r1, #0x80000000  \r\n"        "strne  r1, [%0, %2, lsl #2] \r\n"        /* */        "msr    cpsr_c, r2           \r\n"        : : "r"(&CORE_CTL(CPU)), "r"(&CORE_MESSAGE(CPU)), "r" (othercore)        : "r1", "r2", "r3");#else    CORE_CTL(othercore) = PROC_WAKE;#endif}