firmware/target/arm/imx31/crt0.o:     file format elf32-littlearm

Disassembly of section .text:

00000000 <undef_instr_handler>:
   0:	e1a0000e 	mov	r0, lr
   4:	e3a01000 	mov	r1, #0	; 0x0
   8:	eafffffe 	b	34 <UIE>

0000000c <reserved_handler>:
   c:	ebfffffe 	bl	0 <irq_handler>
  10:	e1b0f00e 	movs	pc, lr

00000014 <prefetch_abort_handler>:
  14:	e24e0004 	sub	r0, lr, #4	; 0x4
  18:	e3a01001 	mov	r1, #1	; 0x1
  1c:	eafffffe 	b	34 <UIE>

00000020 <data_abort_handler>:
  20:	e24e0008 	sub	r0, lr, #8	; 0x8
  24:	e3a01002 	mov	r1, #2	; 0x2
  28:	eafffffe 	b	34 <UIE>

0000002c <irqz>:
  2c:	ebfffffe 	bl	0 <irq_handler>

00000030 <fiqz>:
  30:	ebfffffe 	bl	0 <fiq_handler>

00000034 <UIE>:
  34:	eafffffe 	b	34 <UIE>
	...

00000438 <irq_stack>:
	...
Disassembly of section .init.text:

00000000 <start>:
   0:	ea00000f 	b	44 <newstart>
	...

00000044 <newstart>:
  44:	e329f0d3 	msr	CPSR_fc, #211	; 0xd3
  48:	e59f21b0 	ldr	r2, [pc, #432]	; 200 <.init.text+0x200>
  4c:	e59f31b0 	ldr	r3, [pc, #432]	; 204 <.init.text+0x204>
  50:	e3a04000 	mov	r4, #0	; 0x0
  54:	e1530002 	cmp	r3, r2
  58:	84824004 	strhi	r4, [r2], #4
  5c:	8a000013 	bhi	54 <newstart+0x10>
  60:	e59fd1a0 	ldr	sp, [pc, #416]	; 208 <.init.text+0x208>
  64:	e1a0300d 	mov	r3, sp
  68:	e59f219c 	ldr	r2, [pc, #412]	; 20c <.init.text+0x20c>
  6c:	e59f419c 	ldr	r4, [pc, #412]	; 210 <.init.text+0x210>
  70:	e1530002 	cmp	r3, r2
  74:	84824004 	strhi	r4, [r2], #4
  78:	8a00001a 	bhi	70 <newstart+0x2c>
  7c:	e3a00000 	mov	r0, #0	; 0x0
  80:	ee070f17 	mcr	15, 0, r0, cr7, cr7, {0}
  84:	ee080f17 	mcr	15, 0, r0, cr8, cr7, {0}
  88:	ee070f9a 	mcr	15, 0, r0, cr7, cr10, {4}
  8c:	e3a00155 	mov	r0, #1073741845	; 0x40000015
  90:	ee0f0f92 	mcr	15, 0, r0, cr15, cr2, {4}
  94:	e3a00203 	mov	r0, #805306368	; 0x30000000
  98:	e5902100 	ldr	r2, [r0, #256]
  9c:	e3c22001 	bic	r2, r2, #1	; 0x1
  a0:	e5802100 	str	r2, [r0, #256]
  a4:	e5901104 	ldr	r1, [r0, #260]
  a8:	e20114fe 	and	r1, r1, #-33554432	; 0xfe000000
  ac:	e59f2160 	ldr	r2, [pc, #352]	; 214 <.init.text+0x214>
  b0:	e1811002 	orr	r1, r1, r2
  b4:	e5801104 	str	r1, [r0, #260]
  b8:	e3a010ff 	mov	r1, #255	; 0xff
  bc:	e580177c 	str	r1, [r0, #1916]

000000c0 <L2_loop>:
  c0:	e590277c 	ldr	r2, [r0, #1916]
  c4:	e3520000 	cmp	r2, #0	; 0x0
  c8:	1a00002e 	bne	c0 <L2_loop>
  cc:	e3a000d2 	mov	r0, #210	; 0xd2
  d0:	e129f000 	msr	CPSR_fc, r0
  d4:	e59fd13c 	ldr	sp, [pc, #316]	; 218 <.init.text+0x218>
  d8:	e3a000d1 	mov	r0, #209	; 0xd1
  dc:	e129f000 	msr	CPSR_fc, r0
  e0:	e59fd134 	ldr	sp, [pc, #308]	; 21c <.init.text+0x21c>
  e4:	e3a000d7 	mov	r0, #215	; 0xd7
  e8:	e129f000 	msr	CPSR_fc, r0
  ec:	e59fd124 	ldr	sp, [pc, #292]	; 218 <.init.text+0x218>
  f0:	e3a000db 	mov	r0, #219	; 0xdb
  f4:	e129f000 	msr	CPSR_fc, r0
  f8:	e59fd118 	ldr	sp, [pc, #280]	; 218 <.init.text+0x218>
  fc:	e3a000d3 	mov	r0, #211	; 0xd3
 100:	e129f000 	msr	CPSR_fc, r0
 104:	e59fd0fc 	ldr	sp, [pc, #252]	; 208 <.init.text+0x208>
 108:	e59f3110 	ldr	r3, [pc, #272]	; 220 <.init.text+0x220>
 10c:	e3a01000 	mov	r1, #0	; 0x0
 110:	e3a02321 	mov	r2, #-2080374784	; 0x84000000

00000114 <ttbloop>:
 114:	e4831004 	str	r1, [r3], #4
 118:	e1530002 	cmp	r3, r2
 11c:	1a000043 	bne	114 <ttbloop>
 120:	e59f30f8 	ldr	r3, [pc, #248]	; 220 <.init.text+0x220>
 124:	ee023f10 	mcr	15, 0, r3, cr2, cr0, {0}
 128:	e3e03000 	mvn	r3, #0	; 0x0
 12c:	ee033f10 	mcr	15, 0, r3, cr3, cr0, {0}
 130:	e3a01000 	mov	r1, #0	; 0x0
 134:	e59f30e4 	ldr	r3, [pc, #228]	; 220 <.init.text+0x220>
 138:	e3a04321 	mov	r4, #-2080374784	; 0x84000000

0000013c <maploop1>:
 13c:	e1a02001 	mov	r2, r1
 140:	e3822b01 	orr	r2, r2, #1024	; 0x400
 144:	e3822010 	orr	r2, r2, #16	; 0x10
 148:	e3822002 	orr	r2, r2, #2	; 0x2
 14c:	e4832004 	str	r2, [r3], #4
 150:	e2811601 	add	r1, r1, #1048576	; 0x100000
 154:	e1530004 	cmp	r3, r4
 158:	1a00004d 	bne	13c <maploop1>
 15c:	e3a01102 	mov	r1, #-2147483648	; 0x80000000
 160:	e59f30b8 	ldr	r3, [pc, #184]	; 220 <.init.text+0x220>
 164:	e59f40b8 	ldr	r4, [pc, #184]	; 224 <.init.text+0x224>

00000168 <maploop2>:
 168:	e1a02001 	mov	r2, r1
 16c:	e3822b01 	orr	r2, r2, #1024	; 0x400
 170:	e3822010 	orr	r2, r2, #16	; 0x10
 174:	e3822008 	orr	r2, r2, #8	; 0x8
 178:	e3822004 	orr	r2, r2, #4	; 0x4
 17c:	e3822002 	orr	r2, r2, #2	; 0x2
 180:	e4832004 	str	r2, [r3], #4
 184:	e2811601 	add	r1, r1, #1048576	; 0x100000
 188:	e1530004 	cmp	r3, r4
 18c:	1a000058 	bne	168 <maploop2>
 190:	ee113f10 	mrc	15, 0, r3, cr1, cr0, {0}
 194:	e3130004 	tst	r3, #4	; 0x4
 198:	0bfffffe 	bleq	0 <clean_dcache>
 19c:	e3130a01 	tst	r3, #4096	; 0x1000
 1a0:	0bfffffe 	bleq	0 <clean_dcache>
 1a4:	e3a00000 	mov	r0, #0	; 0x0
 1a8:	ee080f17 	mcr	15, 0, r0, cr8, cr7, {0}
 1ac:	ee070f17 	mcr	15, 0, r0, cr7, cr7, {0}
 1b0:	ee110f10 	mrc	15, 0, r0, cr1, cr0, {0}
 1b4:	e3800001 	orr	r0, r0, #1	; 0x1
 1b8:	e3800004 	orr	r0, r0, #4	; 0x4
 1bc:	e3800a01 	orr	r0, r0, #4096	; 0x1000
 1c0:	ee010f10 	mcr	15, 0, r0, cr1, cr0, {0}
 1c4:	e1a00000 	nop			(mov r0,r0)
 1c8:	e1a00000 	nop			(mov r0,r0)
 1cc:	e1a00000 	nop			(mov r0,r0)
 1d0:	e1a00000 	nop			(mov r0,r0)
 1d4:	e3a00000 	mov	r0, #0	; 0x0
 1d8:	e59f1048 	ldr	r1, [pc, #72]	; 228 <.init.text+0x228>
 1dc:	e3a02000 	mov	r2, #0	; 0x0

000001e0 <lp>:
 1e0:	e5913000 	ldr	r3, [r1]
 1e4:	e2811004 	add	r1, r1, #4	; 0x4
 1e8:	e5803000 	str	r3, [r0]
 1ec:	e2800004 	add	r0, r0, #4	; 0x4
 1f0:	e2822001 	add	r2, r2, #1	; 0x1
 1f4:	e3520010 	cmp	r2, #16	; 0x10
 1f8:	1a000076 	bne	1e0 <lp>
 1fc:	ebfffffe 	bl	0 <main>
	...
 210:	deadbeef 	cdple	14, 10, cr11, cr13, cr15, {7}
 214:	00030024 	andeq	r0, r3, r4, lsr #32
 218:	00000438 	andeq	r0, r0, r8, lsr r4
 21c:	00000838 	andeq	r0, r0, r8, lsr r8
 220:	83ffc000 	mvnhis	ip, #0	; 0x0
 224:	83ffc100 	mvnhis	ip, #0	; 0x0
 228:	00000000 	andeq	r0, r0, r0
Disassembly of section .vectors:

00000000 <_vectorstart>:
   0:	e59ff018 	ldr	pc, [pc, #24]	; 20 <vectors>
   4:	e59ff018 	ldr	pc, [pc, #24]	; 24 <vectors+0x4>
   8:	e59ff018 	ldr	pc, [pc, #24]	; 28 <vectors+0x8>
   c:	e59ff018 	ldr	pc, [pc, #24]	; 2c <vectors+0xc>
  10:	e59ff018 	ldr	pc, [pc, #24]	; 30 <vectors+0x10>
  14:	e59ff018 	ldr	pc, [pc, #24]	; 34 <vectors+0x14>
  18:	e59ff018 	ldr	pc, [pc, #24]	; 38 <vectors+0x18>
  1c:	e59ff018 	ldr	pc, [pc, #24]	; 3c <vectors+0x1c>

00000020 <vectors>:
	...
  28:	0000000c 	andeq	r0, r0, ip
  2c:	00000014 	andeq	r0, r0, r4, lsl r0
  30:	00000020 	andeq	r0, r0, r0, lsr #32
  34:	0000000c 	andeq	r0, r0, ip
  38:	0000002c 	andeq	r0, r0, ip, lsr #32
  3c:	00000030 	andeq	r0, r0, r0, lsr r0