void ipod_set_cpu_frequency(void)
{
    /* Check COP status bits 31 and 30 at COP_CTL */
    long cop_status = COP_CTL & ( (1<<31) | (1<<30) );
    
    /* Set bits 27 and 31 in PLL_CONTROL reg */
    PLL_CONTROL |= ( (1<<27) | (1<<31) );
    
    /* Disable IRQ and FIQ in CPSR */
    asm volatile("msr    cpsr_c, #0xd3");
    
    /* Write 0x40000000 to COP_CTL */
    COP_CTL = 0x40000000;
    
    /* Execute four NOPs */
    asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
    
    /* Write 0x4800001f to CPU_CTL */
    CPU_CTL = 0x4800001f;
    
    /* Select 24MHz crystal as RUN source*/
    CLK_SRC = (CLK_SRC & 0xdfffff0f) | (1<<29) | (CLK_SRC_24MHZ<<4);
    
    /* Write 0x4800000f to CPU_CTL */
    CPU_CTL = 0x4800000f;
    
    /* Execute three NOPs */
    asm volatile("nop\n\tnop\n\tnop\n\t");
    
    /* If COP status bits were zero */
    if(cop_status==0){
        /* Execute four NOPs */
        asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
        /* Write 0 to 0x60007004 */
        COP_CTL = 0;
        /* Execute four NOPs */
        asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
    }
    
    /* Enable IRQ and FIQ in CPSR */
    asm volatile("msr    cpsr_c, #0x13");
    
    /* Set bits 0-15 of PLL_CONTROL for desired freq = (25/8)*24MHz */
    PLL_CONTROL = (PLL_CONTROL & 0xffff0000) | 8 | (25 << 8);
    
    /* Set bits 27 and 31 in PLL_CONTROL reg */
    PLL_CONTROL |= ( (1<<27) | (1<<31) );
    
    /* If executing in COP */
    if(CURRENT_CORE == COP)
    {
        /* Write 0x420000c8 to 0x60007004; */
        COP_CTL = 0x420000c8;
    } else {
        /* Write 0x420000c8 to 0x60007000; */
        CPU_CTL = 0x420000c8;
    }
    
    /* Disable IRQ and FIQ in CPSR */
    asm volatile("msr    cpsr_c, #0xd3");
    
    /* Write 0x40000000 to COP_CTL */
    COP_CTL = 0x40000000;
    
    /* Execute four NOPs */
    asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
    
    /* Write 0x4800001f to CPU_CTL */
    CPU_CTL = 0x4800001f;
    
    /* Select PLL as RUN source*/
    CLK_SRC = (CLK_SRC & 0xdfffff0f) | (1<<29) | (CLK_SRC_PLL<<4);
    
    /* Write 0x4800000f to CPU_CTL */
    CPU_CTL = 0x4800000f;
    
    /* Execute four NOPs */
    asm volatile("nop\n\tnop\n\tnop\n\t");
    
    /* If COP status bits were zero */
    if(cop_status==0){
        /* Execute four NOPs */
        asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
        /* Write 0 to 0x60007004 */
        COP_CTL = 0;
        /* Execute four NOPs */
        asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
    }
    
    /* Enable IRQ and FIQ in CPSR */
    asm volatile("msr    cpsr_c, #0x13");
    
    cpu_frequency = 75000000;
}