Part of Slepp's Projects — Pastebin — TURL — Imagebin — Filebin
Feedback -- English French German Japanese
Create Upload Newest Tools Donate
Sign In | Create Account

Paste Actions

Download Raw
Embed
pBox URL
Post to Twitter
Remove Paste

Paste Details

Raw format, 5 years 3 months old, and 660 hits.

Advertising

Miscellany
Thursday, January 31st, 2008 at 7:48:33pm MST 

  1. Linker Script:
  2.     .vectors :
  3.     {
  4.         _vectorsstart = .;
  5.         *(.vectors*);
  6.         _vectorsend = .;
  7.         *(.init.text)
  8.     } > FLASH
  9.  
  10.     _vectorscopy = LOADADDR(.vectors);
  11.  
  12.     .text DRAMORIG:
  13.     {
  14.         loadaddress = .;
  15.         _loadaddress = .;
  16.         . = ALIGN(0x200);
  17.         *(.text*)
  18.         *(.glue_7)
  19.         *(.glue_7t)
  20.         . = ALIGN(0x4);
  21.     } > DRAM AT> FLASH
  22.  
  23.     _textcopy = LOADADDR(.text);
  24.  
  25.     .rodata :
  26.     {
  27.         *(.rodata)  /* problems without this, dunno why */
  28.         *(.rodata*)
  29.         *(.rodata.str1.1)
  30.         *(.rodata.str1.4)
  31.         . = ALIGN(0x4);
  32.     } > DRAM AT> FLASH
  33.  
  34.     .data :
  35.     {
  36.         _datastart = .;
  37.         *(.data*)
  38.         . = ALIGN(0x4);
  39.         _dataend  = .;
  40.     } > DRAM AT> FLASH
  41.  
  42.     /DISCARD/ :
  43.     {
  44.         *(.eh_frame)
  45.     }
  46.  
  47.     .iram :
  48.     {
  49.         _iramstart = .;
  50.         *(.icode)
  51.         *(.irodata)
  52.         *(.idata)
  53.         . = ALIGN(0x4);       
  54.         _iramend = .;
  55.     } > DRAM AT> FLASH
  56.  
  57.     _iramcopy = LOADADDR(.iram);
  58.  
  59.     .ibss :
  60.     {
  61.         _iedata = .;
  62.         *(.ibss)
  63.         . = ALIGN(0x4);
  64.         _iend = .;
  65.     } > DRAM AT> FLASH
  66.  
  67.     .stack :
  68.     {
  69.        *(.stack)
  70.        stackbegin = .;
  71.        . += 0x2000;
  72.        stackend = .;
  73.     } > DRAM AT> FLASH
  74.  
  75.     .bss :
  76.     {
  77.        _edata = .;
  78.         *(.bss*)
  79.         *(COMMON)
  80.         . = ALIGN(0x4);
  81.        _end = .;
  82.     } > DRAM AT> FLASH
  83.  
  84. crt0.s:
  85.  
  86. /***************************************************************************
  87.  *             __________               __   ___.
  88.  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
  89.  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
  90.  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
  91.  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  92.  *                     \/            \/     \/    \/            \/
  93.  * $Id: crt0.S 15581 2007-11-11 19:13:09Z kkurbjun $
  94.  *
  95.  * Copyright (C) 2002 by Linus Nielsen Feltzing
  96.  *
  97.  * All files in this archive are subject to the GNU General Public License.
  98.  * See the file COPYING in the source tree root for full license agreement.
  99.  *
  100.  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  101.  * KIND, either express or implied.
  102.  *
  103.  ****************************************************************************/
  104. #include "config.h"
  105. #include "cpu.h"
  106.  
  107. /* Exception Handlers */
  108. .section .vectors,"x" ,%progbits
  109.     b       start
  110.     ldr     pc, =undef_instr_handler
  111.     ldr     pc, =software_int_handler
  112.     ldr     pc, =prefetch_abort_handler
  113.     ldr     pc, =data_abort_handler
  114.     ldr     pc, =reserved_handler
  115.     ldr     pc, =irq_handler
  116.     ldr     pc, =fiq_handler
  117.  
  118. /* Initialization Section - Linked to Address 0x0 */
  119. .section .init.text,"ax",%progbits
  120.     .global    start
  121. start:
  122.  
  123.     msr     cpsr, #0xd3 /* enter supervisor mode, disable IRQ */
  124.  
  125.     /* Disable the watchdog */
  126.     ldr     r2,=0x00000000
  127.     mov     r1, #0x53000000
  128.     str     r2, [r1]
  129.  
  130.     /* Zero out IBSS */
  131.     ldr     r2, =_iedata
  132.     ldr     r3, =_iend
  133.     mov     r4, #0
  134. 1:
  135.     cmp     r3, r2
  136.     strhi   r4, [r2], #4
  137.     bhi     1b
  138.  
  139.     /* Copy the IRAM */
  140.     ldr    r2, =_iramcopy
  141.     ldr    r3, =_iramstart
  142.     ldr    r4, =_iramend
  143. 1:
  144.     cmp    r4, r3
  145.     ldrhi  r5, [r2], #4
  146.     strhi  r5, [r3], #4
  147.     bhi    1b
  148.  
  149.     /* Initialise bss section to zero */
  150.     ldr    r2, =_edata
  151.     ldr    r3, =_end
  152.     mov    r4, #0
  153. 1:
  154.     cmp    r3, r2
  155.     strhi  r4, [r2], #4
  156.     bhi    1b
  157.    
  158.     /* Set up some stack and munge it with 0xdeadbeef */
  159.     ldr    sp, =stackend
  160.     mov    r3, sp
  161.     ldr    r2, =stackbegin
  162.     ldr    r4, =0xdeadbeef
  163. 1:
  164.     cmp    r3, r2
  165.     strhi  r4, [r2], #4
  166.     bhi    1b
  167.  
  168.     /* set Bus to Asynchronous mode before PLL manipluation */   
  169.     mov r0, #0
  170.     mrc p15, 0, r0, c1, c0, 0
  171.     orr r0, r0, #3<<30
  172.     mcr p15, 0, r0, c1, c0, 0
  173. #if 1
  174.     /* Initial Clock Setup */
  175.     ldr     r2,=0x00000007
  176.     mov     r1, #0x4C000000
  177.     str     r2, [r1,#14]
  178.  
  179.     ldr     r2,=0x0
  180.     str     r2, [r1, #18]
  181.  
  182.     ldr     r2,=0xFFFFFFFF
  183.     str     r2, [r1]
  184.  
  185.     ldr     r2,=0x0003C042
  186.     str     r2, [r1, #8]
  187.  
  188.     nop
  189.     nop
  190.     nop
  191.     nop
  192.     nop
  193.     nop
  194.     nop
  195.     nop
  196.  
  197.     ldr     r2,=0x000C9042
  198.     str     r2, [r1, #4]
  199. #endif
  200.     /* Proper initialization pulled from 0x5070 */
  201.  
  202.     /* BWSCON
  203.      *      Reserved 0
  204.      * Bank 0:
  205.      *      Bus width 01 (16 bit)
  206.      * Bank 1:
  207.      *      Buswidth 00 (8 bit)
  208.      *      Disable wait 0
  209.      *      Not using UB/LB 0
  210.      * Bank 2:
  211.      *      Buswidth 10 (32 bit)
  212.      *      Disable wait 0
  213.      *      Not using UB/LB 0
  214.      * Bank 3:
  215.      *      Buswidth 10 (32 bit)
  216.      *      Disable wait 0
  217.      *      Use UB/LB 1
  218.      * Bank 4:
  219.      *      Buswidth 10 (32 bit)
  220.      *      Disable wait 0
  221.      *      Use UB/LB 1
  222.      * Bank 5:
  223.      *      Buswidth 00 (8 bit)
  224.      *      Disable wait 0
  225.      *      Not using UB/LB 0
  226.      * Bank 6:
  227.      *      Buswidth 10 (32 bit)
  228.      *      Disable wait 0
  229.      *      Not using UB/LB 0
  230.      * Bank 7:
  231.      *      Buswidth 00 (8 bit)
  232.      *      Disable wait 0
  233.      *      Not using UB/LB 0
  234.      */
  235.     ldr     r2,=0x01055102
  236.     mov     r1, #0x48000000
  237.     str     r2, [r1]
  238.  
  239.     /* BANKCON0
  240.      *      Pagemode: normal (1 data) 00
  241.      *      Pagemode access cycle: 2 clocks 00
  242.      *      Address hold: 2 clocks 10
  243.      *      Chip selection hold time: 1 clock 10
  244.      *      Access cycle: 8 clocks 101
  245.      *      Chip select setup time: 1 clock 01
  246.      *      Address setup time: 0 clock 00
  247.      */
  248.     ldr     r2,=0x00000D60
  249.     str     r2, [r1, #4]
  250.  
  251.  
  252.     /* BANKCON1
  253.      *      Pagemode: normal (1 data) 00
  254.      *      Pagemode access cycle: 2 clocks 00
  255.      *      Address hold: 0 clocks 00
  256.      *      Chip selection hold time: 0 clock 00
  257.      *      Access cycle: 1 clocks 000
  258.      *      Chip select setup time: 0 clocks 00
  259.      *      Address setup time: 0 clocks 00
  260.      */
  261.     ldr     r2,=0x00000000
  262.     str     r2, [r1, #8]
  263.  
  264.     /* BANKCON2
  265.      *      Pagemode: normal (1 data) 00
  266.      *      Pagemode access cycle: 2 clocks 00
  267.      *      Address hold: 2 clocks 10
  268.      *      Chip selection hold time: 2 clocks 10
  269.      *      Access cycle: 14 clocks 111
  270.      *      Chip select setup time: 4 clocks 11
  271.      *      Address setup time: 0 clocks 00
  272.      */
  273.     ldr     r2,=0x00001FA0
  274.     str     r2, [r1, #0xC]
  275.  
  276.     /* BANKCON3 */
  277.     ldr     r2,=0x00001D80
  278.     str     r2, [r1, #0x10]
  279.     /* BANKCON4 */
  280.     str     r2, [r1, #0x14]
  281.  
  282.     /* BANKCON5 */
  283.     ldr     r2,=0x00000000
  284.     str     r2, [r1, #0x18]
  285.  
  286.     /* BANKCON6/7
  287.      *      SCAN:   9 bit       01
  288.      *      Trcd:   3 clocks    01
  289.      *      Tcah:   0 clock     00
  290.      *      Tcoh:   0 clock     00
  291.      *      Tacc:   1 clock     000
  292.      *      Tcos:   0 clock     00
  293.      *      Tacs:   0 clock     00
  294.      *      MT:     Sync DRAM   11
  295.      */
  296.     ldr     r2,=0x00018005
  297.     str     r2, [r1, #0x1C]
  298.     /* BANKCON7 */
  299.     str     r2, [r1, #0x20]
  300.  
  301.     /* REFRESH */
  302.     ldr     r2,=0x00980501
  303.     str     r2, [r1, #0x24]
  304.  
  305.     /* BANKSIZE
  306.      *      BK76MAP: 32M/32M    000
  307.      *      Reserved: 0         0 (was 1)
  308.      *      SCLK_EN: always     1 (was 0)
  309.      *      SCKE_EN: disable    0
  310.      *      Reserved: 0         0
  311.      *      BURST_EN: enabled   1
  312.      */
  313.     ldr     r2,=0x00000090
  314.     str     r2, [r1, #0x28]
  315.  
  316.     /* MRSRB6 */
  317.     ldr     r2,=0x00000030
  318.     str     r2, [r1, #0x2C]
  319.     /* MRSRB7 */
  320.     str     r2, [r1, #0x30]
  321.    
  322. #if 0
  323.     /* This next part I am not sure of the purpose */
  324.    
  325.     /* GPACON */
  326.     mov    r2,#0x01FFFCFF
  327.     str    r2,=0x56000000
  328.    
  329.     /* GPADAT */
  330.     mov    r2,#0x01FFFEFF
  331.     str    r2,=0x56000004
  332.  
  333.     /* MRSRB6 */
  334.     mov    r2,#0x00000000
  335.     str    r2,=0x4800002C
  336.  
  337.     /* GPADAT */
  338.     ldr     r2,=0x01FFFFFF
  339.     mov     r1, #0x56000000
  340.     str     r2, [r1, #4]
  341.  
  342.     /* MRSRB6 */
  343.     mov    r2,#0x00000030
  344.     str    r2,=0x4800002C
  345.  
  346.     /* GPACON */
  347.     mov    r2,#0x01FFFFFF
  348.     str    r2,=0x56000000
  349.  
  350.     /* End of the unknown */
  351. #endif
  352.  
  353.     /* get the high part of our execute address */
  354.     ldr    r2, =0xffffff00
  355.     and    r4, pc, r2
  356.  
  357.     /* Copy bootloader to safe area - 0x31000000 */
  358.     ldr    r5, =_textcopy
  359.     ldr    r6, = _dataend
  360.     sub    r0, r6, r5       /* length of loader */
  361.     add    r0, r4, r0     /* r0 points to start of loader */
  362. 1:
  363.     cmp    r5, r6
  364.     ldrcc  r2, [r4], #4
  365.     strcc  r2, [r5], #4
  366.     bcc    1b
  367.  
  368.      /* Set up stack for IRQ mode */
  369.     msr    cpsr_c, #0xd2
  370.     ldr    sp, =irq_stack
  371.     /* Set up stack for FIQ mode */
  372.     msr    cpsr_c, #0xd1
  373.     ldr    sp, =fiq_stack
  374.  
  375.     /* Let abort and undefined modes use IRQ stack */
  376.     msr    cpsr_c, #0xd7
  377.     ldr    sp, =irq_stack
  378.     msr    cpsr_c, #0xdb
  379.     ldr    sp, =irq_stack
  380.     /* Switch to supervisor mode */
  381.     msr    cpsr_c, #0xd3
  382.     ldr    sp, =stackend
  383.  
  384.     .text
  385.     bl     main
  386.     /* main() should never return */
  387.  
  388.     .global irq
  389.     .global fiq
  390.     .global UIE
  391.  
  392. /* All illegal exceptions call into UIE with exception address as first
  393.    parameter. This is calculated differently depending on which exception
  394.    we're in. Second parameter is exception number, used for a string lookup
  395.    in UIE.
  396.  */
  397. undef_instr_handler:
  398.     mov    r0, lr
  399.     mov    r1, #0
  400.     b      UIE
  401.  
  402. /* We run supervisor mode most of the time, and should never see a software
  403.    exception being thrown. Perhaps make it illegal and call UIE?
  404.  */
  405. software_int_handler:
  406. reserved_handler:
  407.     movs   pc, lr
  408.  
  409. prefetch_abort_handler:
  410.     sub    r0, lr, #4
  411.     mov    r1, #1
  412.     b      UIE
  413.  
  414. data_abort_handler:
  415.     sub    r0, lr, #8
  416.     mov    r1, #2
  417.     b      UIE
  418.  
  419. fiq_handler:
  420.     b fiq_handler
  421.  
  422. irq_handler:
  423.     b irq_handler
  424.  
  425. UIE:
  426.     b UIE
  427.  
  428. /* 256 words of IRQ stack */
  429.     .space 256*4
  430. irq_stack:
  431.  
  432. /* 256 words of FIQ stack */
  433.     .space 256*4
  434. fiq_stack:

advertising

Update the Post

Either update this post and resubmit it with changes, or make a new post.

You may also comment on this post.

update paste below
details of the post (optional)

Note: Only the paste content is required, though the following information can be useful to others.

Save name / title?

(space separated, optional)



Please note that information posted here will expire by default in one month. If you do not want it to expire, please set the expiry time above. If it is set to expire, web search engines will not be allowed to index it prior to it expiring. Items that are not marked to expire will be indexable by search engines. Be careful with your passwords. All illegal activities will be reported and any information will be handed over to the authorities, so be good.

worth-right
worth-right