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Miscellany
Tuesday, January 22nd, 2008 at 8:07:30pm UTC 

  1. iRiver H10 5gb
  2.  
  3. *** LATEST ***
  4.  
  5. SVN + Patchv13 + first few mods by Andree (see http://pastebin.com/m30764cd2)
  6. GPO32      21000000
  7. DEV_EN    C2001977
  8. DEV_EN2  00002020
  9. DEV_EN3  0007003F
  10. DEV_INIT1       FC001100
  11. DEV_INIT2       20000000
  12.  
  13. *************
  14.  
  15.  
  16. Pure SVN
  17.  
  18. GPO32      21000000
  19. DEV_EN    C240197F
  20. DEV_EN2  00002020
  21. DEV_EN3  0007003F
  22.  
  23.  
  24. SVN + patch v13 + fiddling with debug_menu.c
  25. GPO32      21000000
  26. DEV_EN    C2001977
  27. DEV_EN2  00002020
  28. DEV_EN3  0007003F
  29. DEV_INIT1       FC001100
  30. DEV_INIT2       20000000
  31.  
  32.  
  33. ************************************************
  34. /***************************************************************************
  35.  *             __________               __   ___.
  36.  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
  37.  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
  38.  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
  39.  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  40.  *                     \/            \/     \/    \/            \/
  41.  * $Id: system-pp502x.c 15818 2007-11-26 23:13:35Z bagder $
  42.  *
  43.  * Copyright (C) 2002 by Alan Korr
  44.  *
  45.  * All files in this archive are subject to the GNU General Public License.
  46.  * See the file COPYING in the source tree root for full license agreement.
  47.  *
  48.  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  49.  * KIND, either express or implied.
  50.  *
  51.  ****************************************************************************/
  52. #include "system.h"
  53. #include "thread.h"
  54. #include "i2s.h"
  55. #include "i2c-pp.h"
  56. #include "as3514.h"
  57. #ifdef HAVE_USBSTACK
  58. #include "usb_drv.h"
  59. #endif
  60.  
  61. #ifndef BOOTLOADER
  62. extern void TIMER1(void);
  63. extern void TIMER2(void);
  64. extern void ipod_mini_button_int(void); /* iPod Mini 1st gen only */
  65. extern void ipod_4g_button_int(void);   /* iPod 4th gen and higher only */
  66. extern void microsd_int(void);          /* Sansa E200 and C200 */
  67. #ifdef SANSA_E200
  68. extern void button_int(void);
  69. extern void clickwheel_int(void);
  70. #endif
  71.  
  72. void irq(void)
  73. {
  74.     if(CURRENT_CORE == CPU)
  75.     {
  76.         if (CPU_INT_STAT & TIMER1_MASK) {
  77.             TIMER1();
  78.         } else if (CPU_INT_STAT & TIMER2_MASK)
  79.             TIMER2();
  80. #if defined(IPOD_MINI) /* Mini 1st gen only, mini 2nd gen uses iPod 4G code */
  81.         else if (CPU_HI_INT_STAT & GPIO0_MASK)
  82.             ipod_mini_button_int();
  83. #elif CONFIG_KEYPAD == IPOD_4G_PAD /* except Mini 1st gen, handled above */
  84.         else if (CPU_HI_INT_STAT & I2C_MASK)
  85.             ipod_4g_button_int();
  86. #elif defined(SANSA_E200)
  87.         else if (CPU_HI_INT_STAT & GPIO0_MASK) {
  88.             if (GPIOA_INT_STAT & 0x80)
  89.                 microsd_int();
  90.         }
  91.         else if (CPU_HI_INT_STAT & GPIO1_MASK) {
  92.             if (GPIOF_INT_STAT & 0xff)
  93.                 button_int();
  94.             if (GPIOH_INT_STAT & 0xc0)
  95.                 clickwheel_int();
  96.         }
  97. #elif defined(SANSA_C200)
  98.         else if (CPU_HI_INT_STAT & GPIO2_MASK) {
  99.             if (GPIOL_INT_STAT & 0x08)
  100.                 microsd_int();
  101.         }
  102. #endif
  103. #ifdef HAVE_USBSTACK
  104.         else if (CPU_INT_STAT & USB_MASK) {
  105.             usb_drv_int();
  106.         }
  107. #endif
  108.     } else {
  109.         if (COP_INT_STAT & TIMER2_MASK)
  110.             TIMER2();
  111.     }
  112. }
  113. #endif /* BOOTLOADER */
  114.  
  115. /* TODO: The following function has been lifted straight from IPL, and
  116.    hence has a lot of numeric addresses used straight. I'd like to use
  117.    #defines for these, but don't know what most of them are for or even what
  118.    they should be named. Because of this I also have no way of knowing how
  119.    to extend the funtions to do alternate cache configurations. */
  120.  
  121. #ifndef BOOTLOADER
  122. void flush_icache(void) ICODE_ATTR;
  123. void flush_icache(void)
  124. {
  125.     if (CACHE_CTL & CACHE_CTL_ENABLE)
  126.     {
  127.         CACHE_OPERATION |= CACHE_OP_FLUSH;
  128.         while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
  129.     }
  130. }
  131.  
  132. void invalidate_icache(void) ICODE_ATTR;
  133. void invalidate_icache(void)
  134. {
  135.     if (CACHE_CTL & CACHE_CTL_ENABLE)
  136.     {
  137.         CACHE_OPERATION |= CACHE_OP_FLUSH | CACHE_OP_INVALIDATE;
  138.         while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
  139.         nop; nop; nop; nop;
  140.     }
  141. }
  142.  
  143. static void init_cache(void)
  144. {
  145. /* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
  146.  
  147.     /* cache init mode */
  148.     CACHE_CTL |= CACHE_CTL_INIT;
  149.  
  150.     /* what's this do? */
  151.     CACHE_PRIORITY |= CURRENT_CORE == CPU ? 0x10 : 0x20;
  152.  
  153.     /* Cache if (addr & mask) >> 16 == (mask & match) >> 16:
  154.      * yes: 0x00000000 - 0x03ffffff
  155.      *  no: 0x04000000 - 0x1fffffff
  156.      * yes: 0x20000000 - 0x23ffffff
  157.      *  no: 0x24000000 - 0x3fffffff
  158.      */
  159.     CACHE_MASK = 0x00001c00;
  160.     CACHE_OPERATION = 0xfc0;
  161.  
  162.     /* enable cache */
  163.     CACHE_CTL |= CACHE_CTL_INIT | CACHE_CTL_ENABLE | CACHE_CTL_RUN;
  164.     nop; nop; nop; nop;
  165. }
  166.  
  167. #ifdef HAVE_ADJUSTABLE_CPU_FREQ
  168. void scale_suspend_core(bool suspend) ICODE_ATTR;
  169. void scale_suspend_core(bool suspend)
  170. {
  171.     unsigned int core = CURRENT_CORE;
  172.     unsigned int othercore = 1 - core;
  173.     static unsigned long proc_bits IBSS_ATTR;
  174.     static int oldstatus IBSS_ATTR;
  175.  
  176.     if (suspend)
  177.     {
  178.         oldstatus = set_interrupt_status(IRQ_FIQ_DISABLED, IRQ_FIQ_STATUS);
  179.         proc_bits = PROC_CTL(othercore) & 0xc0000000;
  180.         PROC_CTL(othercore) = 0x40000000; nop;
  181.         PROC_CTL(core) = 0x48000003; nop;
  182.     }
  183.     else
  184.     {
  185.         PROC_CTL(core) = 0x4800001f; nop;
  186.         if (proc_bits == 0)
  187.             PROC_CTL(othercore) = 0;
  188.         set_interrupt_status(oldstatus, IRQ_FIQ_STATUS);
  189.     }
  190. }
  191.  
  192. void set_cpu_frequency(long frequency) ICODE_ATTR;
  193. void set_cpu_frequency(long frequency)
  194. #else
  195. static void pp_set_cpu_frequency(long frequency)
  196. #endif
  197. {     
  198. #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
  199.     spinlock_lock(&boostctrl_spin);
  200. #endif
  201.  
  202.     switch (frequency)
  203.     {
  204.       /* Note1: The PP5022 PLL must be run at >= 96MHz
  205.        * Bits 20..21 select the post divider (1/2/4/8).
  206.        * PP5026 is similar to PP5022 except it doesn't
  207.        * have this limitation (and the post divider?)
  208.        * Note2: CLOCK_SOURCE is set via 0=32kHz, 1=16MHz,
  209.        * 2=24MHz, 3=33MHz, 4=48MHz, 5=SLOW, 6=FAST, 7=PLL.
  210.        * SLOW = 24MHz / (DIV_SLOW + 1), DIV = Bits 16-19
  211.        * FAST = PLL   / (DIV_FAST + 1), DIV = Bits 20-23 */
  212.       case CPUFREQ_SLEEP:
  213.         cpu_frequency =  CPUFREQ_SLEEP;
  214.         PLL_CONTROL  |=  0x0c000000;
  215.         scale_suspend_core(true);
  216.         CLOCK_SOURCE  =  0x20000000; /* source #1, #2, #3, #4: 32kHz (#2 active) */
  217.         scale_suspend_core(false);
  218.         PLL_CONTROL  &= ~0x80000000; /* disable PLL */
  219.         DEV_INIT2    &= ~INIT_PLL;   /* disable PLL power */
  220.         break;
  221.        
  222.       case CPUFREQ_MAX:
  223.         cpu_frequency = CPUFREQ_MAX;
  224.         DEV_INIT2    |= INIT_PLL;   /* enable PLL power */
  225.         PLL_CONTROL  |= 0x88000000; /* enable PLL */
  226.         scale_suspend_core(true);
  227.         CLOCK_SOURCE  = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
  228.         DEV_TIMING1   = 0x00000303;
  229.         scale_suspend_core(false);
  230. #if   defined(IPOD_MINI2G)
  231.         MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */
  232. #elif defined(IPOD_NANO)
  233.         IDE0_CFG     |= 0x10000000; /* set ">65MHz" bit */
  234. #endif
  235. #if CONFIG_CPU == PP5020
  236.         PLL_CONTROL   = 0x8a020a03; /* 80 MHz = 10/3 * 24MHz */
  237.         PLL_STATUS    = 0xd19b;     /* unlock frequencies > 66MHz */
  238.         PLL_CONTROL   = 0x8a020a03; /* repeat setup */
  239.         udelay(500);                /* wait for relock */
  240. #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
  241.         PLL_CONTROL   = 0x8a121403; /*  80 MHz = (20/3 * 24MHz) / 2 */
  242.         //PLL_CONTROL   = 0x8a121903; /* 100 MHz = (25/3 * 24MHz) / 2 */
  243.         while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
  244. #endif
  245.         scale_suspend_core(true);
  246.         DEV_TIMING1   = 0x00000808;
  247.         //DEV_TIMING1   = 0x00000a0a;
  248.         CLOCK_SOURCE  = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */
  249.         scale_suspend_core(false);
  250.         break;
  251.  
  252.       case CPUFREQ_NORMAL:
  253.         cpu_frequency =  CPUFREQ_NORMAL;
  254.         PLL_CONTROL  |=  0x08000000;
  255.         scale_suspend_core(true);
  256.         CLOCK_SOURCE  =  0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
  257.         DEV_TIMING1   =  0x00000303;
  258. #if   defined(IPOD_MINI2G)
  259.         MLCD_SCLK_DIV =  0x00000000; /* Mono LCD bridge serial clock divider */
  260. #elif defined(IPOD_NANO)
  261.         IDE0_CFG     &= ~0x10000000; /* clear ">65MHz" bit */
  262. #endif
  263.         scale_suspend_core(false);
  264.         PLL_CONTROL  &= ~0x80000000; /* disable PLL */
  265.         DEV_INIT2    &= ~INIT_PLL;   /* disable PLL power */
  266.         break;
  267.  
  268.       default:
  269.         cpu_frequency =  CPUFREQ_DEFAULT;
  270.         PLL_CONTROL  |=  0x08000000;
  271.         scale_suspend_core(true);
  272.         CLOCK_SOURCE  =  0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
  273.         DEV_TIMING1   =  0x00000303;
  274. #if   defined(IPOD_MINI2G)
  275.         MLCD_SCLK_DIV =  0x00000000; /* Mono LCD bridge serial clock divider */
  276. #elif defined(IPOD_NANO)
  277.         IDE0_CFG     &= ~0x10000000; /* clear ">65MHz" bit */
  278. #endif
  279.         scale_suspend_core(false);
  280.         PLL_CONTROL  &= ~0x80000000; /* disable PLL */
  281.         DEV_INIT2    &= ~INIT_PLL;   /* disable PLL power */
  282.         break;
  283.     }
  284.    
  285. #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
  286.     spinlock_unlock(&boostctrl_spin);
  287. #endif
  288. }
  289. #endif /* !BOOTLOADER */
  290.  
  291. void system_init(void)
  292. {
  293. #ifndef BOOTLOADER
  294.     if (CURRENT_CORE == CPU)
  295.     {
  296. #if defined (IRIVER_H10)
  297. /*
  298.         DEV_RS = 0x3ffffef8;
  299.         DEV_RS2 = -1;
  300.         outl(inl(0x70000024) | 0xc0, 0x70000024);
  301.         DEV_RS = 0;
  302.         DEV_RS2 = 0;
  303.         */
  304.         /* set minimum startup configuration */
  305.         DEV_EN         = 0xc2000124; /* DEV_EN1 minimum configuration for startup */
  306.         DEV_EN2        = 0x00002020; /* DEV_EN2 minimum configuration for startup */
  307.         CACHE_PRIORITY = 0x0000003f; /* DEV_EN3 minimum configuration for startup */
  308.         GPO32_VAL      = 0x21000000; /* GPO32_VAL minimum configuration for startup */
  309.         DEV_INIT1      = 0xfc001100; /* DEV_INIT1 minimum configuration for startup */
  310.         DEV_INIT2      = 0x61000000; /* DEV_INIT2 minimum configuration for startup */
  311.  
  312.         /* reset all allowed devices */
  313.         /*
  314.         DEV_RS         = 0x3ffffef8;
  315.         DEV_RS2        = 0xffffffff;
  316.         DEV_RS         = 0x00000000;
  317.         DEV_RS2        = 0x00000000;
  318.         */
  319.                
  320. #elif defined (IPOD_VIDEO)   
  321.         /* set minimum startup configuration */
  322.         DEV_EN         = 0xc2000124; /* DEV_EN1 minimum configuration for startup */
  323.         DEV_EN2        = 0x00000000; /* DEV_EN2 minimum configuration for startup */
  324.         CACHE_PRIORITY = 0x0000003f; /* DEV_EN3 minimum configuration for startup */
  325.         GPO32_VAL      = 0x00004000; /* GPO32_VAL minimum configuration for startup */
  326.         DEV_INIT1      = 0x00000000; /* DEV_INIT1 minimum configuration for startup */
  327.         DEV_INIT2      = 0x40000000; /* DEV_INIT2 minimum configuration for startup */
  328.  
  329.         /* reset all allowed devices */
  330.         DEV_RS         = 0x3ffffef8;
  331.         DEV_RS2        = 0xffffffff;
  332.         DEV_RS         = 0x00000000;
  333.         DEV_RS2        = 0x00000000;
  334. #elif defined (IPOD_NANO)   
  335.         /* set minimum startup configuration */
  336.         DEV_EN         = 0xc2000124; /* DEV_EN1 minimum configuration for startup */
  337.         DEV_EN2        = 0x00002000; /* DEV_EN2 minimum configuration for startup */
  338.         CACHE_PRIORITY = 0x0000003f; /* DEV_EN3 minimum configuration for startup */
  339.         GPO32_VAL      = 0x50000000; /* GPO32_VAL minimum configuration for startup */
  340.         DEV_INIT1      = 0xa8000000; /* DEV_INIT1 minimum configuration for startup */
  341.         DEV_INIT2      = 0x40000000; /* DEV_INIT2 minimum configuration for startup */
  342.  
  343.         /* reset all allowed devices */
  344.         DEV_RS         = 0x3ffffef8;
  345.         DEV_RS2        = 0xffffdfff;
  346.         DEV_RS         = 0x00000000;
  347.         DEV_RS2        = 0x00000000;
  348. #elif defined(SANSA_C200) || defined (SANSA_E200)   
  349.         /* set minimum startup configuration */
  350.         DEV_EN         = 0xc4004124; /* DEV_EN1 minimum configuration for startup */
  351.         DEV_EN2        = 0x00000000; /* DEV_EN2 minimum configuration for startup */
  352.         CACHE_PRIORITY = 0x0000003f; /* DEV_EN3 minimum configuration for startup */
  353.         GPO32_VAL      = 0x10000000; /* GPO32_VAL minimum configuration for startup */
  354.         DEV_INIT1      = 0x54000000; /* DEV_INIT1 minimum configuration for startup */
  355.         DEV_INIT2      = 0x40000000; /* DEV_INIT2 minimum configuration for startup */
  356.  
  357.         /* reset all allowed devices */
  358.         DEV_RS         = 0x3bfffef8;
  359.         DEV_RS2        = 0xffffffff;
  360.         DEV_RS         = 0x00000000;
  361.         DEV_RS2        = 0x00000000;
  362. #endif
  363.  
  364. #if !defined(SANSA_E200) && !defined(SANSA_C200)
  365.         /* Remap the flash ROM on CPU, keep hidden from COP:
  366.          * 0x00000000-0x3fffffff = 0x20000000-0x23ffffff */
  367.         MMAP1_LOGICAL  = 0x20003c00;
  368.         MMAP1_PHYSICAL = 0x00003084 |
  369.             MMAP_PHYS_READ_MASK | MMAP_PHYS_WRITE_MASK |
  370.             MMAP_PHYS_DATA_MASK | MMAP_PHYS_CODE_MASK;
  371. #endif
  372.  
  373.         /* disable all irqs */
  374.         COP_HI_INT_CLR      = -1;
  375.         CPU_HI_INT_CLR      = -1;
  376.         HI_INT_FORCED_CLR   = -1;
  377.        
  378.         COP_INT_CLR         = -1;
  379.         CPU_INT_CLR         = -1;
  380.         INT_FORCED_CLR      = -1;
  381.  
  382.         GPIOA_INT_EN        = 0;
  383.         GPIOB_INT_EN        = 0;
  384.         GPIOC_INT_EN        = 0;
  385.         GPIOD_INT_EN        = 0;
  386.         GPIOE_INT_EN        = 0;
  387.         GPIOF_INT_EN        = 0;
  388.         GPIOG_INT_EN        = 0;
  389.         GPIOH_INT_EN        = 0;
  390.         GPIOI_INT_EN        = 0;
  391.         GPIOJ_INT_EN        = 0;
  392.         GPIOK_INT_EN        = 0;
  393.         GPIOL_INT_EN        = 0;
  394.  
  395. #if defined(SANSA_E200) || defined(SANSA_C200)
  396.         /* outl(0x00000000, 0x6000b000); */
  397.         outl(inl(0x6000a000) | 0x80000000, 0x6000a000); /* Init DMA controller? */
  398. #endif
  399.  
  400. #ifdef HAVE_ADJUSTABLE_CPU_FREQ
  401. #if NUM_CORES > 1
  402.         cpu_boost_init();
  403. #endif
  404. #else
  405.         pp_set_cpu_frequency(CPUFREQ_MAX);
  406. #endif
  407.     }
  408.  
  409.     init_cache();
  410. #endif /* BOOTLOADER */
  411. }
  412.  
  413. void system_reboot(void)
  414. {
  415.     /* Reboot */
  416. #if defined(SANSA_E200) || defined(SANSA_C200)
  417.     CACHE_CTL &= ~CACHE_CTL_VECT_REMAP;
  418.  
  419.     pp_i2c_send(AS3514_I2C_ADDR, DCDC15, 0x0); /* backlight off */
  420.  
  421.     /* Magic used by the c200 OF: 0x23066000
  422.        Magic used by the c200 BL: 0x23066b7b
  423.        In both cases, the OF executes these 2 commands from iram. */
  424.     STRAP_OPT_A = 0x23066b7b;
  425.     DEV_RS = DEV_SYSTEM;
  426. #else
  427.     DEV_RS |= DEV_SYSTEM;
  428. #endif
  429. }
  430.  
  431. int system_memory_guard(int newmode)
  432. {
  433.     (void)newmode;
  434.     return 0;
  435. }

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