Anonymous

Assume that the control unit delay is 5ns. What is the minimum clock period for this step?

T6: shr (:= n != 0 -> C(31..0) <- 0#C<31..1>: n <- n-1; Shr));


Diagrams available at: http://ece.uprm.edu/~nayda/Courses/Inel4215S06/Lectures/Ch4CSDA.pdf