rendered paste bodyIndex: firmware/export/pp5020.h
===================================================================
--- firmware/export/pp5020.h (revision 15090)
+++ firmware/export/pp5020.h (working copy)
@@ -117,8 +117,9 @@
/* Device Controller */
#define DEV_RS (*(volatile unsigned long *)(0x60006004))
-#define DEV_OFF_MASK (*(volatile unsigned long *)(0x60006008))
+#define DEV_RS2 (*(volatile unsigned long *)(0x60006008))
#define DEV_EN (*(volatile unsigned long *)(0x6000600c))
+#define DEV_EN2 (*(volatile unsigned long *)(0x60006010))
#define DEV_SYSTEM 0x00000004
#define DEV_SER0 0x00000040
@@ -137,6 +138,7 @@
#define CLOCK_SOURCE (*(volatile unsigned long *)(0x60006020))
#define PLL_CONTROL (*(volatile unsigned long *)(0x60006034))
#define PLL_STATUS (*(volatile unsigned long *)(0x6000603c))
+#define ADC_CLOCK_SRC (*(volatile unsigned long *)(0x60006094))
#define CLCD_CLOCK_SRC (*(volatile unsigned long *)(0x600060a0))
/* Processors Control */
@@ -299,7 +301,8 @@
#define RAM_TYPE_MASK 0x000000c0
#define ROM_TYPE_MASK 0x00000008
-#define DEV_INIT (*(volatile unsigned long *)(0x70000020))
+#define DEV_INIT1 (*(volatile unsigned long *)(0x70000010))
+#define DEV_INIT2 (*(volatile unsigned long *)(0x70000020))
/* some timing that needs to be handled during clock setup */
#define DEV_TIMING1 (*(volatile unsigned long *)(0x70000034))
#define XMB_NOR_CFG (*(volatile unsigned long *)(0x70000038))
Index: firmware/target/arm/usb-fw-pp502x.c
===================================================================
--- firmware/target/arm/usb-fw-pp502x.c (revision 15090)
+++ firmware/target/arm/usb-fw-pp502x.c (working copy)
@@ -44,7 +44,7 @@
DEV_RS |= DEV_USB; /* reset usb start */
DEV_RS &=~DEV_USB;/* reset usb end */
- DEV_INIT |= INIT_USB;
+ DEV_INIT2 |= INIT_USB;
while ((inl(0x70000028) & 0x80) == 0);
UDC_PORTSC1 |= PORTSCX_PORT_RESET;
@@ -70,7 +70,7 @@
/* Note from IPL source (referring to next 5 lines of code:
THIS NEEDS TO BE CHANGED ONCE THERE IS KERNEL USB */
- DEV_INIT |= INIT_USB;
+ DEV_INIT2 |= INIT_USB;
DEV_EN |= DEV_USB;
while ((inl(0x70000028) & 0x80) == 0);
outl(inl(0x70000028) | 0x2, 0x70000028);
Index: firmware/target/arm/wmcodec-pp.c
===================================================================
--- firmware/target/arm/wmcodec-pp.c (revision 15090)
+++ firmware/target/arm/wmcodec-pp.c (working copy)
@@ -46,7 +46,7 @@
#ifdef CPU_PP502x
/* normal outputs for CDI and I2S pin groups */
- DEV_INIT &= ~0x300;
+ DEV_INIT2 &= ~0x300;
/*mini2?*/
outl(inl(0x70000010) & ~0x3000000, 0x70000010);
Index: firmware/target/arm/sandisk/power-c200_e200.c
===================================================================
--- firmware/target/arm/sandisk/power-c200_e200.c (revision 15090)
+++ firmware/target/arm/sandisk/power-c200_e200.c (working copy)
@@ -85,7 +85,7 @@
#if defined(SANSA_E200)
outl(inl(0x70000084) | 0x1, 0x70000084);
#else /* SANSA_C200 */
- DEV_INIT &= ~0x800;
+ DEV_INIT2 &= ~0x800;
#endif
udelay(5);
@@ -120,7 +120,7 @@
#if defined (SANSA_E200)
outl(inl(0x70000084) & ~0x1, 0x70000084);
#else
- DEV_INIT |= 0x800;
+ DEV_INIT2 |= 0x800;
#endif
}
Index: firmware/target/arm/sandisk/sansa-c200/lcd-c200.c
===================================================================
--- firmware/target/arm/sandisk/sansa-c200/lcd-c200.c (revision 15090)
+++ firmware/target/arm/sandisk/sansa-c200/lcd-c200.c (working copy)
@@ -88,7 +88,7 @@
outl(inl(0x70000010) & ~0xfc000000, 0x70000010);
outl(inl(0x70000010), 0x70000010);
- DEV_INIT &= ~0x400;
+ DEV_INIT2 &= ~0x400;
udelay(10000);
LCD1_CONTROL &= ~0x4;
Index: firmware/target/arm/sandisk/sansa-e200/lcd-e200.c
===================================================================
--- firmware/target/arm/sandisk/sansa-e200/lcd-e200.c (revision 15090)
+++ firmware/target/arm/sandisk/sansa-e200/lcd-e200.c (working copy)
@@ -372,7 +372,7 @@
/* Controller init */
outl((inl(0x70000084) | (1 << 28)), 0x70000084);
outl((inl(0x70000080) & ~(1 << 28)), 0x70000080);
- outl(((inl(0x70000010) & (0x03ffffff)) | (0x15 << 26)), 0x70000010);
+ DEV_INIT1 = ( (DEV_INIT1 & 0x03ffffff) | (0x15 << 26) );
outl(((inl(0x70000014) & (0x0fffffff)) | (0x5 << 28)), 0x70000014);
outl((inl(0x70000020) & ~(0x3 << 10)), 0x70000020);
DEV_EN |= DEV_LCD; /* Enable controller */
Index: firmware/target/arm/iriver/h10/adc-target.h
===================================================================
--- firmware/target/arm/iriver/h10/adc-target.h (revision 15090)
+++ firmware/target/arm/iriver/h10/adc-target.h (working copy)
@@ -19,9 +19,6 @@
#ifndef _ADC_TARGET_H_
#define _ADC_TARGET_H_
-#define ADC_ENABLE_ADDR (*(volatile unsigned long*)(0x70000010))
-#define ADC_ENABLE 0x1100
-
#define ADC_ADDR (*(volatile unsigned long*)(0x7000ad00))
#define ADC_STATUS (*(volatile unsigned long*)(0x7000ad04))
#define ADC_DATA_1 (*(volatile unsigned long*)(0x7000ad20))
Index: firmware/target/arm/iriver/h10/adc-h10.c
===================================================================
--- firmware/target/arm/iriver/h10/adc-h10.c (revision 15090)
+++ firmware/target/arm/iriver/h10/adc-h10.c (working copy)
@@ -25,29 +25,21 @@
static unsigned short adcdata[NUM_ADC_CHANNELS];
-/* Scan ADC so that adcdata[channel] gets updated */
+/* Scan ADC so that adcdata[channel] gets updated. */
unsigned short adc_scan(int channel)
{
unsigned int adc_data_1;
unsigned int adc_data_2;
- /* Initialise */
- ADC_ADDR=0x130;
- ADC_STATUS=0; /* 4 bytes, 1 per channel. Each byte is 0 if the channel is
- off, 0x40 if the channel is on */
+ /* Start conversion */
+ ADC_ADDR |= 0x80000000;
- /* Enable Channel */
- ADC_ADDR |= (0x1000000<<channel);
+ /* Wait for conversion to complete */
+ while((ADC_STATUS & (0x40<<8*channel))==0);
- /* Start? */
- ADC_ADDR |= 0x20000000;
- ADC_ADDR |= 0x80000000;
-
-#if 0
- /* wait for ADC ready. THIS IS NOT WORKING (locks up) */
- while(ADC_STATUS & (0x40 << (channel*8))); /* add loop protection here */
-#endif
-
+ /* Stop conversion */
+ ADC_ADDR &=~ 0x80000000;
+
/* ADC_DATA_1 and ADC_DATA_2 are both four bytes, one byte per channel.
For each channel, ADC_DATA_1 stores the 8-bit msb, ADC_DATA_2 stores the
2-bit lsb (in bits 0 and 1). Each channel is 10 bits total. */
@@ -56,6 +48,13 @@
adcdata[channel] = (adc_data_1<<2 | adc_data_2);
+ /* ADC values read low if PLL is enabled */
+ if(PLL_CONTROL & 0x80000000){
+ adcdata[channel] += 0x14;
+ if(adcdata[channel] > 0x400)
+ adcdata[channel] = 0x400;
+ }
+
return adcdata[channel];
}
@@ -79,25 +78,64 @@
}
}
+/* Figured out from how the OF does things */
void adc_init(void)
{
+ ADC_INIT |= 1;
+ ADC_INIT |= 0x40000000;
+ udelay(100);
+
+ /* Reset ADC */
+ DEV_RS2 |= 0x20;
+ udelay(100);
+
+ DEV_RS2 &=~ 0x20;
+ udelay(100);
+
/* Enable ADC */
- ADC_ENABLE_ADDR |= ADC_ENABLE;
-
- /* Initialise */
- ADC_INIT=0;
+ DEV_EN2 |= 0x20;
+ udelay(100);
+ ADC_CLOCK_SRC |= 0x3;
+ udelay(100);
+
+ ADC_ADDR |= 0x40;
+ ADC_ADDR |= 0x20000000;
+ udelay(100);
+
+ ADC_INIT;
+ ADC_INIT = 0;
+ udelay(100);
+
+ ADC_STATUS = 0;
+
+ /* Enable channel 0 (battery) */
+ DEV_INIT1 &=~0x3;
+ ADC_ADDR |= 0x1000000;
+ ADC_STATUS |= 0x20;
+
+ /* Enable channel 1 (unknown, temperature?) */
+ DEV_INIT1 &=~30;
+ ADC_ADDR |= 0x2000000;
+ ADC_STATUS |= 0x2000;
+
+ /* Enable channel 2 (remote) */
+ DEV_INIT1 &=~0x300;
+ DEV_INIT1 |= 0x100;
+ ADC_ADDR |= 0x4000000;
+ ADC_STATUS |= 0x200000;
+
+ /* Enable channel 3 (scroll pad) */
+ DEV_INIT1 &=~0x3000;
+ DEV_INIT1 |= 0x1000;
+ ADC_ADDR |= 0x8000000;
+ ADC_STATUS |= 0x20000000;
+
/* Force a scan of all channels to get initial values */
adc_scan(ADC_BATTERY);
adc_scan(ADC_UNKNOWN_1);
adc_scan(ADC_REMOTE);
adc_scan(ADC_SCROLLPAD);
-
- /* FIXME: The ADC sometimes reads 0 for the battery
- voltage for the first few seconds. It would be better to fix this by
- figuring out how to use the ADC properly. Until then, work around the
- problem by waiting until it reads a proper value*/
- while(adc_scan(ADC_UNREG_POWER)==0);
tick_add_task(adc_tick);
}
Index: firmware/target/arm/system-pp502x.c
===================================================================
--- firmware/target/arm/system-pp502x.c (revision 15090)
+++ firmware/target/arm/system-pp502x.c (working copy)
@@ -203,17 +203,17 @@
{
#if defined(SANSA_E200) || defined(SANSA_C200)
/* Reset all devices */
- DEV_OFF_MASK |= 0x20;
+ DEV_RS2 |= 0x20;
DEV_RS = 0x3bfffef8;
- DEV_OFF_MASK = -1;
+ DEV_RS2 = -1;
DEV_RS = 0;
- DEV_OFF_MASK = 0;
+ DEV_RS2 = 0;
#elif defined (IRIVER_H10)
DEV_RS = 0x3ffffef8;
- DEV_OFF_MASK = -1;
+ DEV_RS2 = -1;
outl(inl(0x70000024) | 0xc0, 0x70000024);
DEV_RS = 0;
- DEV_OFF_MASK = 0;
+ DEV_RS2 = 0;
#endif
#if !defined(SANSA_E200) && !defined(SANSA_C200)
@@ -252,7 +252,7 @@
outl(inl(0x6000a000) | 0x80000000, 0x6000a000); /* Init DMA controller? */
#endif
- DEV_INIT |= 1 << 30; /* enable PLL power */
+ DEV_INIT2 |= 1 << 30; /* enable PLL power */
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
#if NUM_CORES > 1
Index: firmware/drivers/audio/as3514.c
===================================================================
--- firmware/drivers/audio/as3514.c (revision 15090)
+++ firmware/drivers/audio/as3514.c (working copy)
@@ -138,7 +138,7 @@
i2c_init();
/* normal outputs for CDI and I2S pin groups */
- DEV_INIT &= ~0x300;
+ DEV_INIT2 &= ~0x300;
/*mini2?*/
outl(inl(0x70000010) & ~0x3000000, 0x70000010);