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Untitled
Saturday, October 13th, 2007 at 11:34:50am UTC 

  1. Index: firmware/export/pp5020.h
  2. ===================================================================
  3. --- firmware/export/pp5020.h    (revision 15090)
  4. +++ firmware/export/pp5020.h    (working copy)
  5. @@ -117,8 +117,9 @@
  6.  
  7.  /* Device Controller */
  8.  #define DEV_RS       (*(volatile unsigned long *)(0x60006004))
  9. -#define DEV_OFF_MASK (*(volatile unsigned long *)(0x60006008))
  10. +#define DEV_RS2      (*(volatile unsigned long *)(0x60006008))
  11.  #define DEV_EN       (*(volatile unsigned long *)(0x6000600c))
  12. +#define DEV_EN2      (*(volatile unsigned long *)(0x60006010))
  13.  
  14.  #define DEV_SYSTEM      0x00000004
  15.  #define DEV_SER0        0x00000040
  16. @@ -137,6 +138,7 @@
  17.  #define CLOCK_SOURCE    (*(volatile unsigned long *)(0x60006020))
  18.  #define PLL_CONTROL     (*(volatile unsigned long *)(0x60006034))
  19.  #define PLL_STATUS      (*(volatile unsigned long *)(0x6000603c))
  20. +#define ADC_CLOCK_SRC   (*(volatile unsigned long *)(0x60006094))
  21.  #define CLCD_CLOCK_SRC  (*(volatile unsigned long *)(0x600060a0))
  22.  
  23.  /* Processors Control */
  24. @@ -299,7 +301,8 @@
  25.  #define RAM_TYPE_MASK    0x000000c0
  26.  #define ROM_TYPE_MASK    0x00000008
  27.  
  28. -#define DEV_INIT         (*(volatile unsigned long *)(0x70000020))
  29. +#define DEV_INIT1        (*(volatile unsigned long *)(0x70000010))
  30. +#define DEV_INIT2        (*(volatile unsigned long *)(0x70000020))
  31.  /* some timing that needs to be handled during clock setup */
  32.  #define DEV_TIMING1      (*(volatile unsigned long *)(0x70000034))
  33.  #define XMB_NOR_CFG      (*(volatile unsigned long *)(0x70000038))
  34. Index: firmware/target/arm/usb-fw-pp502x.c
  35. ===================================================================
  36. --- firmware/target/arm/usb-fw-pp502x.c (revision 15090)
  37. +++ firmware/target/arm/usb-fw-pp502x.c (working copy)
  38. @@ -44,7 +44,7 @@
  39.      DEV_RS |= DEV_USB; /* reset usb start */ 
  40.      DEV_RS &=~DEV_USB;/* reset usb end */ 
  41.  
  42. -    DEV_INIT |= INIT_USB;
  43. +    DEV_INIT2 |= INIT_USB;
  44.      while ((inl(0x70000028) & 0x80) == 0);
  45.  
  46.      UDC_PORTSC1 |= PORTSCX_PORT_RESET; 
  47. @@ -70,7 +70,7 @@
  48.  
  49.      /* Note from IPL source (referring to next 5 lines of code: 
  50.         THIS NEEDS TO BE CHANGED ONCE THERE IS KERNEL USB */ 
  51. -    DEV_INIT |= INIT_USB;
  52. +    DEV_INIT2 |= INIT_USB;
  53.      DEV_EN |= DEV_USB;
  54.      while ((inl(0x70000028) & 0x80) == 0);
  55.      outl(inl(0x70000028) | 0x2, 0x70000028);
  56. Index: firmware/target/arm/wmcodec-pp.c
  57. ===================================================================
  58. --- firmware/target/arm/wmcodec-pp.c    (revision 15090)
  59. +++ firmware/target/arm/wmcodec-pp.c    (working copy)
  60. @@ -46,7 +46,7 @@
  61.  
  62.  #ifdef CPU_PP502x
  63.      /* normal outputs for CDI and I2S pin groups */
  64. -    DEV_INIT &= ~0x300;
  65. +    DEV_INIT2 &= ~0x300;
  66.  
  67.      /*mini2?*/
  68.      outl(inl(0x70000010) & ~0x3000000, 0x70000010);
  69. Index: firmware/target/arm/sandisk/power-c200_e200.c
  70. ===================================================================
  71. --- firmware/target/arm/sandisk/power-c200_e200.c       (revision 15090)
  72. +++ firmware/target/arm/sandisk/power-c200_e200.c       (working copy)
  73. @@ -85,7 +85,7 @@
  74.  #if defined(SANSA_E200)
  75.              outl(inl(0x70000084) | 0x1, 0x70000084);
  76.  #else /* SANSA_C200 */
  77. -            DEV_INIT &= ~0x800;
  78. +            DEV_INIT2 &= ~0x800;
  79.  #endif
  80.              udelay(5);
  81.  
  82. @@ -120,7 +120,7 @@
  83.  #if defined (SANSA_E200)
  84.              outl(inl(0x70000084) & ~0x1, 0x70000084);
  85.  #else
  86. -            DEV_INIT |= 0x800;
  87. +            DEV_INIT2 |= 0x800;
  88.  #endif
  89.          }
  90.  
  91. Index: firmware/target/arm/sandisk/sansa-c200/lcd-c200.c
  92. ===================================================================
  93. --- firmware/target/arm/sandisk/sansa-c200/lcd-c200.c   (revision 15090)
  94. +++ firmware/target/arm/sandisk/sansa-c200/lcd-c200.c   (working copy)
  95. @@ -88,7 +88,7 @@
  96.      outl(inl(0x70000010) & ~0xfc000000, 0x70000010);
  97.      outl(inl(0x70000010), 0x70000010);
  98.  
  99. -    DEV_INIT &= ~0x400;
  100. +    DEV_INIT2 &= ~0x400;
  101.      udelay(10000);
  102.      
  103.      LCD1_CONTROL &= ~0x4;
  104. Index: firmware/target/arm/sandisk/sansa-e200/lcd-e200.c
  105. ===================================================================
  106. --- firmware/target/arm/sandisk/sansa-e200/lcd-e200.c   (revision 15090)
  107. +++ firmware/target/arm/sandisk/sansa-e200/lcd-e200.c   (working copy)
  108. @@ -372,7 +372,7 @@
  109.  /* Controller init */
  110.      outl((inl(0x70000084) | (1 << 28)), 0x70000084);
  111.      outl((inl(0x70000080) & ~(1 << 28)), 0x70000080);
  112. -    outl(((inl(0x70000010) & (0x03ffffff)) | (0x15 << 26)), 0x70000010);
  113. +    DEV_INIT1 = ( (DEV_INIT1 & 0x03ffffff) | (0x15 << 26) );
  114.      outl(((inl(0x70000014) & (0x0fffffff)) | (0x5 << 28)), 0x70000014);
  115.      outl((inl(0x70000020) & ~(0x3 << 10)), 0x70000020);
  116.      DEV_EN |= DEV_LCD; /* Enable controller */
  117. Index: firmware/target/arm/iriver/h10/adc-target.h
  118. ===================================================================
  119. --- firmware/target/arm/iriver/h10/adc-target.h (revision 15090)
  120. +++ firmware/target/arm/iriver/h10/adc-target.h (working copy)
  121. @@ -19,9 +19,6 @@
  122.  #ifndef _ADC_TARGET_H_
  123.  #define _ADC_TARGET_H_
  124.  
  125. -#define ADC_ENABLE_ADDR     (*(volatile unsigned long*)(0x70000010))
  126. -#define ADC_ENABLE          0x1100
  127. -
  128.  #define ADC_ADDR            (*(volatile unsigned long*)(0x7000ad00))
  129.  #define ADC_STATUS          (*(volatile unsigned long*)(0x7000ad04))
  130.  #define ADC_DATA_1          (*(volatile unsigned long*)(0x7000ad20))
  131. Index: firmware/target/arm/iriver/h10/adc-h10.c
  132. ===================================================================
  133. --- firmware/target/arm/iriver/h10/adc-h10.c    (revision 15090)
  134. +++ firmware/target/arm/iriver/h10/adc-h10.c    (working copy)
  135. @@ -25,29 +25,21 @@
  136.  
  137.  static unsigned short adcdata[NUM_ADC_CHANNELS];
  138.  
  139. -/* Scan ADC so that adcdata[channel] gets updated */
  140. +/* Scan ADC so that adcdata[channel] gets updated. */
  141.  unsigned short adc_scan(int channel)
  142.  {
  143.      unsigned int adc_data_1;
  144.      unsigned int adc_data_2;
  145.  
  146. -    /* Initialise */
  147. -    ADC_ADDR=0x130;
  148. -    ADC_STATUS=0;   /* 4 bytes, 1 per channel. Each byte is 0 if the channel is
  149. -                       off, 0x40 if the channel is on */
  150. +    /* Start conversion */
  151. +    ADC_ADDR |= 0x80000000;
  152.      
  153. -    /* Enable Channel */
  154. -    ADC_ADDR |= (0x1000000<<channel);
  155. +    /* Wait for conversion to complete */
  156. +    while((ADC_STATUS & (0x40<<8*channel))==0);
  157.      
  158. -    /* Start? */
  159. -    ADC_ADDR |= 0x20000000;
  160. -    ADC_ADDR |= 0x80000000;
  161. -
  162. -#if 0
  163. -    /* wait for ADC ready. THIS IS NOT WORKING (locks up) */
  164. -    while(ADC_STATUS & (0x40 << (channel*8))); /* add loop protection here */
  165. -#endif
  166. -
  167. +    /* Stop conversion */
  168. +    ADC_ADDR &=~ 0x80000000;
  169. +   
  170.      /* ADC_DATA_1 and ADC_DATA_2 are both four bytes, one byte per channel.
  171.         For each channel, ADC_DATA_1 stores the 8-bit msb, ADC_DATA_2 stores the
  172.         2-bit lsb (in bits 0 and 1). Each channel is 10 bits total. */
  173. @@ -56,6 +48,13 @@
  174.      
  175.      adcdata[channel] = (adc_data_1<<2 | adc_data_2);
  176.      
  177. +    /* ADC values read low if PLL is enabled */
  178. +    if(PLL_CONTROL & 0x80000000){
  179. +        adcdata[channel] += 0x14;
  180. +        if(adcdata[channel] > 0x400)
  181. +            adcdata[channel] = 0x400;
  182. +    }
  183. +   
  184.      return adcdata[channel];
  185.  }
  186.  
  187. @@ -79,25 +78,64 @@
  188.      }
  189.  }
  190.  
  191. +/* Figured out from how the OF does things */
  192.  void adc_init(void)
  193.  {
  194. +    ADC_INIT |= 1;
  195. +    ADC_INIT |= 0x40000000;
  196. +    udelay(100);
  197. +   
  198. +    /* Reset ADC */
  199. +    DEV_RS2 |= 0x20;
  200. +    udelay(100);
  201. +   
  202. +    DEV_RS2 &=~ 0x20;
  203. +    udelay(100);
  204. +   
  205.      /* Enable ADC */
  206. -    ADC_ENABLE_ADDR |= ADC_ENABLE;
  207. -   
  208. -    /* Initialise */
  209. -    ADC_INIT=0;
  210. +    DEV_EN2 |= 0x20;
  211. +    udelay(100);
  212.  
  213. +    ADC_CLOCK_SRC |= 0x3;
  214. +    udelay(100);
  215. +
  216. +    ADC_ADDR |= 0x40;
  217. +    ADC_ADDR |= 0x20000000;
  218. +    udelay(100);
  219. +
  220. +    ADC_INIT;
  221. +    ADC_INIT = 0;
  222. +    udelay(100);
  223. +
  224. +    ADC_STATUS = 0;
  225. +
  226. +    /* Enable channel 0 (battery) */
  227. +    DEV_INIT1  &=~0x3;
  228. +    ADC_ADDR   |= 0x1000000;
  229. +    ADC_STATUS |= 0x20;
  230. +
  231. +    /* Enable channel 1 (unknown, temperature?) */
  232. +    DEV_INIT1  &=~30;
  233. +    ADC_ADDR   |= 0x2000000;
  234. +    ADC_STATUS |= 0x2000;
  235. +
  236. +    /* Enable channel 2 (remote) */
  237. +    DEV_INIT1  &=~0x300;
  238. +    DEV_INIT1  |= 0x100;
  239. +    ADC_ADDR   |= 0x4000000;
  240. +    ADC_STATUS |= 0x200000;
  241. +
  242. +    /* Enable channel 3 (scroll pad) */
  243. +    DEV_INIT1  &=~0x3000;
  244. +    DEV_INIT1  |= 0x1000;
  245. +    ADC_ADDR   |= 0x8000000;
  246. +    ADC_STATUS |= 0x20000000;
  247. +
  248.      /* Force a scan of all channels to get initial values */
  249.      adc_scan(ADC_BATTERY);
  250.      adc_scan(ADC_UNKNOWN_1);
  251.      adc_scan(ADC_REMOTE);
  252.      adc_scan(ADC_SCROLLPAD);
  253. -   
  254. -    /* FIXME: The ADC sometimes reads 0 for the battery
  255. -       voltage for the first few seconds. It would be better to fix this by
  256. -       figuring out how to use the ADC properly. Until then, work around the
  257. -       problem by waiting until it reads a proper value*/
  258. -    while(adc_scan(ADC_UNREG_POWER)==0);
  259.  
  260.      tick_add_task(adc_tick);
  261.  }
  262. Index: firmware/target/arm/system-pp502x.c
  263. ===================================================================
  264. --- firmware/target/arm/system-pp502x.c (revision 15090)
  265. +++ firmware/target/arm/system-pp502x.c (working copy)
  266. @@ -203,17 +203,17 @@
  267.      {
  268.  #if defined(SANSA_E200) || defined(SANSA_C200)
  269.          /* Reset all devices */
  270. -        DEV_OFF_MASK |= 0x20;
  271. +        DEV_RS2 |= 0x20;
  272.          DEV_RS = 0x3bfffef8;
  273. -        DEV_OFF_MASK = -1;
  274. +        DEV_RS2 = -1;
  275.          DEV_RS = 0;
  276. -        DEV_OFF_MASK = 0;
  277. +        DEV_RS2 = 0;
  278.   #elif defined (IRIVER_H10)
  279.          DEV_RS = 0x3ffffef8;
  280. -        DEV_OFF_MASK = -1;
  281. +        DEV_RS2 = -1;
  282.          outl(inl(0x70000024) | 0xc0, 0x70000024);
  283.          DEV_RS = 0;
  284. -        DEV_OFF_MASK = 0;
  285. +        DEV_RS2 = 0;
  286.  #endif
  287.  
  288.  #if !defined(SANSA_E200) && !defined(SANSA_C200)
  289. @@ -252,7 +252,7 @@
  290.          outl(inl(0x6000a000) | 0x80000000, 0x6000a000); /* Init DMA controller? */
  291.  #endif
  292.  
  293. -        DEV_INIT |= 1 << 30; /* enable PLL power */
  294. +        DEV_INIT2 |= 1 << 30; /* enable PLL power */
  295.  
  296.  #ifdef HAVE_ADJUSTABLE_CPU_FREQ
  297.  #if NUM_CORES > 1
  298. Index: firmware/drivers/audio/as3514.c
  299. ===================================================================
  300. --- firmware/drivers/audio/as3514.c     (revision 15090)
  301. +++ firmware/drivers/audio/as3514.c     (working copy)
  302. @@ -138,7 +138,7 @@
  303.      i2c_init();
  304.  
  305.      /* normal outputs for CDI and I2S pin groups */
  306. -    DEV_INIT &= ~0x300;
  307. +    DEV_INIT2 &= ~0x300;
  308.  
  309.      /*mini2?*/
  310.      outl(inl(0x70000010) & ~0x3000000, 0x70000010);

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