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Anonymous
Tuesday, July 31st, 2007 at 4:20:34pm UTC 

  1. Index: apps/debug_menu.c
  2. ===================================================================
  3. --- apps/debug_menu.c   (revision 14099)
  4. +++ apps/debug_menu.c   (working copy)
  5. @@ -636,7 +636,29 @@
  6.      lcd_clear_display();
  7.  
  8.      lcd_puts(0, line++, "[Hardware info]");
  9. -
  10. +        lcd_puts(0, line++, "test1");
  11. +        lcd_update();
  12. +       
  13. +        set_cpu_frequency(CPUFREQ_SLEEP);
  14. +       
  15. +        asm (
  16. +        "mrs     r2, CPSR            \n"
  17. +        "orr     r0, r2, #0xc0       \n" /* disable IRQ and FIQ */
  18. +        "msr     CPSR_c, r0          \n"
  19. +        "mov     r0, #0x0            \n"
  20. +        "mov     r1, #0x4000         \n"
  21. +        "1:                          \n"
  22. +        "add     r0, r0, #0x1        \n"
  23. +        "cmp     r0, r1              \n"
  24. +        "bcc     1b                  \n"
  25. +        "msr     CPSR_c, r2          \n" /* reset IRQ and FIQ state */
  26. +        );
  27. +       
  28. +        set_cpu_frequency(CPUFREQ_NORMAL);
  29. +       
  30. +        lcd_puts(0, line++, "test2");
  31. +        lcd_update();
  32. +   
  33.  #ifdef IPOD_ARCH
  34.      snprintf(buf, sizeof(buf), "HW rev: 0x%08lx", IPOD_HW_REVISION);
  35.      lcd_puts(0, line++, buf);
  36. Index: firmware/target/arm/system-target.h
  37. ===================================================================
  38. --- firmware/target/arm/system-target.h (revision 14099)
  39. +++ firmware/target/arm/system-target.h (working copy)
  40. @@ -32,6 +32,7 @@
  41.  #define CPUFREQ_MAX     80000000
  42.  
  43.  #else /* PP5022, PP5024 */
  44. +#define CPUFREQ_SLEEP      32768
  45.  #define CPUFREQ_DEFAULT 24000000
  46.  #define CPUFREQ_NORMAL  30000000
  47.  #define CPUFREQ_MAX     80000000
  48. Index: firmware/target/arm/system-pp502x.c
  49. ===================================================================
  50. --- firmware/target/arm/system-pp502x.c (revision 14099)
  51. +++ firmware/target/arm/system-pp502x.c (working copy)
  52. @@ -107,7 +107,6 @@
  53.  #endif
  54.  {
  55.      unsigned long clcd_clock_src;
  56. -    bool use_pll = true;
  57.  
  58.  #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
  59.      /* Using mutex or spinlock isn't safe here. */
  60. @@ -121,31 +120,39 @@
  61.      cpu_frequency = frequency;
  62.      clcd_clock_src = CLCD_CLOCK_SRC; /* save selected color LCD clock source */
  63.  
  64. -    CLOCK_SOURCE = (CLOCK_SOURCE & ~0xf000000f) | 0x10000002;
  65. -                                /* set clock source 1 to 24MHz and select it */
  66. -    CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
  67. -
  68.      switch (frequency)
  69.      {
  70.  #if CONFIG_CPU == PP5020
  71.        case CPUFREQ_MAX:
  72. -        DEV_TIMING1 = 0x00000808;
  73. -        PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */
  74. -        PLL_STATUS  = 0xd19b;     /* unlock frequencies > 66MHz */
  75. -        PLL_CONTROL = 0x8a020a03; /* repeat setup */
  76. -        udelay(500);              /* wait for relock */
  77. +        CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
  78. +        CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
  79. +        DEV_TIMING1  = 0x00000808;
  80. +        PLL_CONTROL  = 0x8a020a03;  /* 10/3 * 24MHz */
  81. +        PLL_STATUS   = 0xd19b;      /* unlock frequencies > 66MHz */
  82. +        PLL_CONTROL  = 0x8a020a03;  /* repeat setup */
  83. +        udelay(500);                /* wait for relock */
  84.          break;
  85.  
  86.        case CPUFREQ_NORMAL:
  87. -        DEV_TIMING1 = 0x00000303;
  88. -        PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */
  89. -        udelay(500);              /* wait for relock */
  90. +        CLOCK_SOURCE = 0x10007772;   /* source #1: 24MHz, #2, #3, #4: PLL */
  91. +        CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
  92. +        DEV_TIMING1  = 0x00000303;
  93. +        PLL_CONTROL  = 0x8a020504;  /* 5/4 * 24MHz */
  94. +        udelay(500);                /* wait for relock */
  95.          break;
  96.  
  97. +      case CPUFREQ_SLEEP:
  98. +        CLOCK_SOURCE = 0x10002202;  /* source #2: 32kHz, #1, #3, #4: 24MHz */
  99. +        CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
  100. +        PLL_CONTROL &= ~0x80000000; /* disable PLL */
  101. +        udelay(10000);              /* let 32kHz source stabilize? */
  102. +        break;
  103. +
  104.        default:
  105. -        DEV_TIMING1 = 0x00000303;
  106. +        CLOCK_SOURCE = 0x10002222;  /* source #1, #2, #3, #4: 24MHz */
  107. +        CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
  108. +        DEV_TIMING1  = 0x00000303;
  109.          PLL_CONTROL &= ~0x80000000; /* disable PLL */
  110. -        use_pll = false;
  111.          cpu_frequency = CPUFREQ_DEFAULT;
  112.          break;
  113.  
  114. @@ -155,29 +162,40 @@
  115.         * PP5026 is similar to PP5022 except it doesn't
  116.         * have this limitation (and the post divider?) */
  117.        case CPUFREQ_MAX:
  118. -        DEV_TIMING1 = 0x00000808;
  119. -        PLL_CONTROL = 0x8a121403; /* (20/3 * 24MHz) / 2 */
  120. +        CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
  121. +        CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
  122. +        DEV_TIMING1  = 0x00000808;
  123. +        PLL_CONTROL  = 0x8a121403;  /* (20/3 * 24MHz) / 2 */
  124.          udelay(250);
  125.          while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
  126.          break;
  127.  
  128.        case CPUFREQ_NORMAL:
  129. -        DEV_TIMING1 = 0x00000303;
  130. -        PLL_CONTROL = 0x8a220501; /* (5/1 * 24MHz) / 4 */
  131. +        CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
  132. +        CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
  133. +        DEV_TIMING1  = 0x00000303;
  134. +        PLL_CONTROL  = 0x8a220501;  /* (5/1 * 24MHz) / 4 */
  135.          udelay(250);
  136.          while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
  137.          break;
  138.  
  139. +      case CPUFREQ_SLEEP:
  140. +        CLOCK_SOURCE = 0x10002202;  /* source #2: 32kHz, #1, #3, #4: 24MHz */
  141. +        CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
  142. +        PLL_CONTROL &= ~0x80000000; /* disable PLL */
  143. +        udelay(10000);              /* let 32kHz source stabilize? */
  144. +        break;
  145. +
  146.        default:
  147. -        DEV_TIMING1 = 0x00000303;
  148. +        CLOCK_SOURCE = 0x10002222;  /* source #1, #2, #3, #4: 24MHz */
  149. +        CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
  150. +        DEV_TIMING1  = 0x00000303;
  151.          PLL_CONTROL &= ~0x80000000; /* disable PLL */
  152. -        use_pll = false;
  153.          cpu_frequency = CPUFREQ_DEFAULT;
  154.          break;
  155.  #endif
  156.      }
  157. -    if (use_pll)                  /* set clock source 2 to PLL and select it */
  158. -        CLOCK_SOURCE = (CLOCK_SOURCE & ~0xf00000f0) | 0x20000070;
  159. +    CLOCK_SOURCE = (CLOCK_SOURCE&~0xf000000)|0x20000000;  /* select source #2 */
  160.  
  161.      CLCD_CLOCK_SRC;             /* dummy read (to sync the write pipeline??) */
  162.      CLCD_CLOCK_SRC = clcd_clock_src; /* restore saved value */

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