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Mine
Tuesday, July 31st, 2007 at 2:33:40pm UTC 

  1. Index: firmware/target/arm/system-target.h
  2. ===================================================================
  3. --- firmware/target/arm/system-target.h (revision 14099)
  4. +++ firmware/target/arm/system-target.h (working copy)
  5. @@ -32,6 +32,7 @@
  6.  #define CPUFREQ_MAX     80000000
  7.  
  8.  #else /* PP5022, PP5024 */
  9. +#define CPUFREQ_SLEEP      32768
  10.  #define CPUFREQ_DEFAULT 24000000
  11.  #define CPUFREQ_NORMAL  30000000
  12.  #define CPUFREQ_MAX     80000000
  13. Index: firmware/target/arm/system-pp502x.c
  14. ===================================================================
  15. --- firmware/target/arm/system-pp502x.c (revision 14099)
  16. +++ firmware/target/arm/system-pp502x.c (working copy)
  17. @@ -107,7 +107,6 @@
  18.  #endif
  19.  {
  20.      unsigned long clcd_clock_src;
  21. -    bool use_pll = true;
  22.  
  23.  #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
  24.      /* Using mutex or spinlock isn't safe here. */
  25. @@ -120,32 +119,37 @@
  26.  
  27.      cpu_frequency = frequency;
  28.      clcd_clock_src = CLCD_CLOCK_SRC; /* save selected color LCD clock source */
  29. -
  30. -    CLOCK_SOURCE = (CLOCK_SOURCE & ~0xf000000f) | 0x10000002;
  31. -                                /* set clock source 1 to 24MHz and select it */
  32.      CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
  33.  
  34.      switch (frequency)
  35.      {
  36.  #if CONFIG_CPU == PP5020
  37.        case CPUFREQ_MAX:
  38. -        DEV_TIMING1 = 0x00000808;
  39. -        PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */
  40. -        PLL_STATUS  = 0xd19b;     /* unlock frequencies > 66MHz */
  41. -        PLL_CONTROL = 0x8a020a03; /* repeat setup */
  42. -        udelay(500);              /* wait for relock */
  43. +        CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
  44. +        DEV_TIMING1  = 0x00000808;
  45. +        PLL_CONTROL  = 0x8a020a03;  /* 10/3 * 24MHz */
  46. +        PLL_STATUS   = 0xd19b;      /* unlock frequencies > 66MHz */
  47. +        PLL_CONTROL  = 0x8a020a03;  /* repeat setup */
  48. +        udelay(500);                /* wait for relock */
  49.          break;
  50.  
  51.        case CPUFREQ_NORMAL:
  52. -        DEV_TIMING1 = 0x00000303;
  53. -        PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */
  54. -        udelay(500);              /* wait for relock */
  55. +        CLOCK_SOURCE = 0x10007772;   /* source #1: 24MHz, #2, #3, #4: PLL */
  56. +        DEV_TIMING1  = 0x00000303;
  57. +        PLL_CONTROL  = 0x8a020504;  /* 5/4 * 24MHz */
  58. +        udelay(500);                /* wait for relock */
  59.          break;
  60.  
  61. +      case CPUFREQ_SLEEP:
  62. +        CLOCK_SOURCE = 0x10002202;  /* source #2: 32kHz, #1, #3, #4: 24MHz */
  63. +        PLL_CONTROL &= ~0x80000000; /* disable PLL */
  64. +        udelay(10000);              /* let 32kHz source stabilize? */
  65. +        break;
  66. +
  67.        default:
  68. -        DEV_TIMING1 = 0x00000303;
  69. +        CLOCK_SOURCE = 0x10002222;  /* source #1, #2, #3, #4: 24MHz */
  70. +        DEV_TIMING1  = 0x00000303;
  71.          PLL_CONTROL &= ~0x80000000; /* disable PLL */
  72. -        use_pll = false;
  73.          cpu_frequency = CPUFREQ_DEFAULT;
  74.          break;
  75.  
  76. @@ -155,29 +159,36 @@
  77.         * PP5026 is similar to PP5022 except it doesn't
  78.         * have this limitation (and the post divider?) */
  79.        case CPUFREQ_MAX:
  80. -        DEV_TIMING1 = 0x00000808;
  81. -        PLL_CONTROL = 0x8a121403; /* (20/3 * 24MHz) / 2 */
  82. +        CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
  83. +        DEV_TIMING1  = 0x00000808;
  84. +        PLL_CONTROL  = 0x8a121403;  /* (20/3 * 24MHz) / 2 */
  85.          udelay(250);
  86.          while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
  87.          break;
  88.  
  89.        case CPUFREQ_NORMAL:
  90. -        DEV_TIMING1 = 0x00000303;
  91. -        PLL_CONTROL = 0x8a220501; /* (5/1 * 24MHz) / 4 */
  92. +        CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
  93. +        DEV_TIMING1  = 0x00000303;
  94. +        PLL_CONTROL  = 0x8a220501;  /* (5/1 * 24MHz) / 4 */
  95.          udelay(250);
  96.          while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
  97.          break;
  98.  
  99. +      case CPUFREQ_SLEEP:
  100. +        CLOCK_SOURCE = 0x10002202;  /* source #2: 32kHz, #1, #3, #4: 24MHz */
  101. +        PLL_CONTROL &= ~0x80000000; /* disable PLL */
  102. +        udelay(10000);              /* let 32kHz source stabilize? */
  103. +        break;
  104. +
  105.        default:
  106. -        DEV_TIMING1 = 0x00000303;
  107. +        CLOCK_SOURCE = 0x10002222;  /* source #1, #2, #3, #4: 24MHz */
  108. +        DEV_TIMING1  = 0x00000303;
  109.          PLL_CONTROL &= ~0x80000000; /* disable PLL */
  110. -        use_pll = false;
  111.          cpu_frequency = CPUFREQ_DEFAULT;
  112.          break;
  113.  #endif
  114.      }
  115. -    if (use_pll)                  /* set clock source 2 to PLL and select it */
  116. -        CLOCK_SOURCE = (CLOCK_SOURCE & ~0xf00000f0) | 0x20000070;
  117. +    CLOCK_SOURCE = (CLOCK_SOURCE&~0xf000000)|0x20000000;  /* select source #2 */
  118.  
  119.      CLCD_CLOCK_SRC;             /* dummy read (to sync the write pipeline??) */
  120.      CLCD_CLOCK_SRC = clcd_clock_src; /* restore saved value */

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