Level 4 user:
Writes new modules
input:
none
output:
module spec file
tools used:
text editor
Level 3 user:
Makes new arrangements of existing modules
stage 1: generate FPGA spec
input:
module spec files (a specific directory?) (read as reference info)
output:
an fpga spec file which contains information on all modules used
tools used:
text editor initially, later a config editor that can read the module
specs and work interactively
stage 2: generate an FPGA file
input:
FPGA spec files
module spec files
module VHDL
top level VHDL template
output:
a bitstream file with additional data:
'o' section: configuration options (per module, with defaults)
'v' section: current values for each option (per instance)
't' section: ram template for translating 'v' into 'w' (per module)
'w' section: config ram contents - 1K bytes, packed binary (or we might generate it later)
tools:
make - controls the overall process
fpga-preprocessor - reads FPGA spec, module spec, and templates, generates top level VHDL and 'o', 't', and 'v' files
FPGA toolchain (xilinx) - reads top level VHDL and other VHDL, generates basic bitfile
fpgs-postprocessor - reads bitfile, merges 'o', 'v', and 't' sections, generates 'w' section (or we might generate the 'w' section at load time)
Level 2 user:
Chooses settings for an existing configuration
input:
an FPGA file with suitable extra blocks of data ("o", "v", and "t" above)
output:
an FPGA file with same 'o' and 't' section, modified 'v' section, and corresponding 'w' section (1K RAM config data)
tools used:
A nice-looking GUI that allows the user to select between different options for the modules that exist in the FPGA. For example, choosing to enable a stepgen or not. If there is a 'w' section in the file, the editor would regenerate it from the 'v' and 't' sections when saving the modified file
level 1 user:
Loads a configuration and manipulates it within the limitations of HAL (exported pins are fixed by the config)
input:
an FPGA file with at least a 'w' section ('o'. 'v', and 't' are ignored) (alternatively, there might be no
'w' section, and the loader would generate it from 'v' and 't')
tools used:
bitfile loader