VHDL step generator

entity stepgen is
    generic (
	asize : integer := 48;
	rsize : integer := 32;
	tsize : integer := 12
    );
    port (
	clock : in std_logic;
--	ibus : in std_logic_vector(31 downto 0);
--	obus : out std_logic_vector(31 downto 0);
--	loadsteprate : in std_logic;
--	loadaccum : in std_logic;
--	loadstepmode : in std_logic;
--	loaddirsetuptime : in std_logic;
--	loaddirholdtime : in std_logic;
--	loadpulsewidth : in std_logic;
--	readsteprate : in std_logic;
--	readaccum : in std_logic;
--	readstepmode : in std_logic;
--	readdirsetuptime : in std_logic;
--	readdirholdtime : in std_logic;
--	readpulsewidth : in std_logic;
	rate : in std_logic_vector ( rsize-1 downto 0 );
	-- step pulse length in clocks - minimum 1
	len : in std_logic_vector ( tsize-1 downto 0 );
	-- hold time - minimum 1, actual time is value + 1
	hold :  in std_logic_vector ( tsize-1 downto 0 );
	-- setup time - minimum 0, actual time is value + 2	
	setup : in std_logic_vector ( tsize-1 downto 0 );
	stepout : buffer std_logic;
	dirout : buffer std_logic;
	stepup : buffer std_logic;
	stepdown : buffer std_logic;
	phasea : buffer std_logic := '0';
	phaseb : buffer std_logic := '0'
    );
end stepgen;

architecture behavioral of stepgen is

    constant pickoff_bit: integer := rsize + 1;

    signal accum: std_logic_vector ( asize-1 downto 0 ) := (others => '0');
    alias pickoff: std_logic is accum(pickoff_bit);
    signal nextaccum: std_logic_vector ( asize-1 downto 0 );
    alias nextpickoff: std_logic is nextaccum(pickoff_bit);
    alias dirreq: std_logic is rate(rsize-1);
    signal ddshold: std_logic;
    signal stepreq : std_logic;
    signal dirhold: std_logic;
    signal dirsetup: std_logic;
    signal holdin: std_logic;
    signal dirchange: std_logic;

begin
    StepDDS:
	process (clock, ddshold, rate, accum, nextaccum)
	begin
	    nextaccum <= signed(accum) + signed(rate);
	    if clock'event and clock = '1' then
		if ddshold = '0' then
		    accum <= nextaccum;
		    stepreq <= pickoff xor nextpickoff;
		else
		    stepreq <= '0';
		end if;
	    end if;

	end process;

    Timing:
	process (clock, stepreq, stepout, dirreq, dirout, dirchange, dirsetup, dirhold)
	begin
	    -- combinatorial
		holdin <= stepreq or stepout;
		dirchange <= dirreq xor dirout;
		ddshold <= dirchange or dirsetup;
	    -- clocked
	    if clock'event and clock = '1' then
		if dirhold = '0' and stepreq = '0' then
		    dirout <= dirreq;
		end if;
	    end if;
	end process;

    Output:
	process (clock, stepreq, stepout, dirout, phasea, phaseb)
	begin
	    -- conbinatorial
		stepup <= stepout and not dirout;
		stepdown <= stepout and dirout;
	    -- clocked
	    if clock'event and clock = '1' then
		if stepreq = '1' then
		    phasea <= phaseb xor dirout;
		    phaseb <= phasea xor not dirout;
		end if;
	    end if;
	end process;

    StepTimer: oneshot
	generic map ( tsize )
	port map (
		input => stepreq,
		output => stepout,
		clock => clock,
		duration => len
	);

    HoldTimer: oneshot
	generic map ( tsize )
	port map (
		input => holdin,
		output => dirhold,
		clock => clock,
		duration => hold
	);

    SetupTimer: oneshot
	generic map ( tsize )
	port map (
		input => dirchange,
		output => dirsetup,
		clock => clock,
		duration => setup
	);

end behavioral;