VHDL oneshot

entity oneshot is
    generic ( size: integer := 2 );
    port (
	duration: in std_logic_vector (size-1 downto 0);
	input: in std_logic;
	output: buffer std_logic;
	clock: in std_logic
    );
end oneshot;

architecture behavioral of oneshot is
    -- internal signals
    signal count: std_logic_vector ( size-1 downto 0) := (others => '0');
    signal muxout: std_logic_vector ( size downto 0);
    alias  muxoutlo: std_logic_vector (size-1 downto 0) is muxout (size-1 downto 0);
    alias  muxouthi: std_logic is muxout(size);
    signal nextcount: std_logic_vector ( size downto 0);
    alias  nextcountlo: std_logic_vector (size-1 downto 0) is nextcount (size-1 downto 0);
    alias  nextcounthi: std_logic is nextcount(size);

begin
    OneShot:
	process (clock, input, duration, count, muxout, nextcount)
	begin
	    if input = '1'  then
		muxoutlo <= duration;
	    else
		muxoutlo <= count;
	    end if;
	    muxouthi <= '0';
	    nextcount <= muxout - 1;
	    if clock'event and clock = '1' then
		if nextcounthi /= '1' then
		    count <= nextcountlo;
		end if;
		output <= not nextcounthi;
	    end if;
	end process;

end behavioral;