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Mine
Wednesday, January 31st, 2007 at 1:27:09am UTC 

  1. void ipod_set_cpu_frequency(void)
  2. {
  3.     /* Check COP status bits 31 and 30 at COP_CTL */
  4.     long cop_status = COP_CTL & ( (1<<31) | (1<<30) );
  5.    
  6.     /* Set bits 27 and 31 in PLL_CONTROL reg */
  7.     PLL_CONTROL |= ( (1<<27) | (1<<31) );
  8.    
  9.     /* Disable IRQ and FIQ in CPSR */
  10.     asm volatile("msr    cpsr_c, #0xd3");
  11.    
  12.     /* Write 0x40000000 to COP_CTL */
  13.     COP_CTL = 0x40000000;
  14.    
  15.     /* Execute four NOPs */
  16.     asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
  17.    
  18.     /* Write 0x4800001f to CPU_CTL */
  19.     CPU_CTL = 0x4800001f;
  20.    
  21.     /* Select 24MHz crystal as RUN source*/
  22.     CLK_SRC = (CLK_SRC & 0xdfffff0f) | (1<<29) | (CLK_SRC_24MHZ<<4);
  23.    
  24.     /* Write 0x4800000f to CPU_CTL */
  25.     CPU_CTL = 0x4800000f;
  26.    
  27.     /* Execute three NOPs */
  28.     asm volatile("nop\n\tnop\n\tnop\n\t");
  29.    
  30.     /* If COP status bits were zero */
  31.     if(cop_status==0){
  32.         /* Execute four NOPs */
  33.         asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
  34.         /* Write 0 to 0x60007004 */
  35.         COP_CTL = 0;
  36.         /* Execute four NOPs */
  37.         asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
  38.     }
  39.    
  40.     /* Enable IRQ and FIQ in CPSR */
  41.     asm volatile("msr    cpsr_c, #0x13");
  42.    
  43.     /* Set bits 0-15 of PLL_CONTROL for desired freq = (25/8)*24MHz */
  44.     PLL_CONTROL = (PLL_CONTROL & 0xffff0000) | 8 | (25 << 8);
  45.    
  46.     /* Set bits 27 and 31 in PLL_CONTROL reg */
  47.     PLL_CONTROL |= ( (1<<27) | (1<<31) );
  48.    
  49.     /* If executing in COP */
  50.     if(CURRENT_CORE == COP)
  51.     {
  52.         /* Write 0x420000c8 to 0x60007004; */
  53.         COP_CTL = 0x420000c8;
  54.     } else {
  55.         /* Write 0x420000c8 to 0x60007000; */
  56.         CPU_CTL = 0x420000c8;
  57.     }
  58.    
  59.     /* Disable IRQ and FIQ in CPSR */
  60.     asm volatile("msr    cpsr_c, #0xd3");
  61.    
  62.     /* Write 0x40000000 to COP_CTL */
  63.     COP_CTL = 0x40000000;
  64.    
  65.     /* Execute four NOPs */
  66.     asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
  67.    
  68.     /* Write 0x4800001f to CPU_CTL */
  69.     CPU_CTL = 0x4800001f;
  70.    
  71.     /* Select PLL as RUN source*/
  72.     CLK_SRC = (CLK_SRC & 0xdfffff0f) | (1<<29) | (CLK_SRC_PLL<<4);
  73.    
  74.     /* Write 0x4800000f to CPU_CTL */
  75.     CPU_CTL = 0x4800000f;
  76.    
  77.     /* Execute four NOPs */
  78.     asm volatile("nop\n\tnop\n\tnop\n\t");
  79.    
  80.     /* If COP status bits were zero */
  81.     if(cop_status==0){
  82.         /* Execute four NOPs */
  83.         asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
  84.         /* Write 0 to 0x60007004 */
  85.         COP_CTL = 0;
  86.         /* Execute four NOPs */
  87.         asm volatile("nop\n\tnop\n\tnop\n\tnop\n\t");
  88.     }
  89.    
  90.     /* Enable IRQ and FIQ in CPSR */
  91.     asm volatile("msr    cpsr_c, #0x13");
  92.    
  93.     cpu_frequency = 75000000;
  94. }

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