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Sunday, December 10th, 2006 at 3:52:22pm UTC 

  1. /***************************************************************************
  2.  *             __________               __   ___.
  3.  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
  4.  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
  5.  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
  6.  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  7.  *                     \/            \/     \/    \/            \/
  8.  * $Id: crt0-pp.S,v 1.2 2006/11/22 00:49:16 dan_a Exp $
  9.  *
  10.  * Copyright (C) 2002 by Linus Nielsen Feltzing
  11.  *
  12.  * All files in this archive are subject to the GNU General Public License.
  13.  * See the file COPYING in the source tree root for full license agreement.
  14.  *
  15.  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16.  * KIND, either express or implied.
  17.  *
  18.  ****************************************************************************/
  19. #include "config.h"
  20. #include "cpu.h"
  21.  
  22.     .section .init.text,"ax",%progbits
  23.  
  24.     .global    start
  25. start:
  26.  
  27. /* PortalPlayer bootloader and startup code based on startup.s from the iPodLinux
  28.  * loader
  29.  *
  30.  * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
  31.  * Copyright (c) 2005, Bernard Leach <[email protected]>
  32.  *
  33.  */
  34. #if CONFIG_CPU == PP5002
  35.     .equ    PROC_ID,  0xc4000000
  36.     .equ    COP_CTRL, 0xcf004058
  37.     .equ    COP_STATUS, 0xcf004050
  38.     .equ    IIS_CONFIG, 0xc0002500
  39.     .equ    SLEEP,    0xca
  40.     .equ    WAKE,     0xce
  41.     .equ    SLEEPING, 0x4000
  42. #else
  43.     .equ    PROC_ID,  0x60000000
  44.     .equ    COP_CTRL, 0x60007004
  45.     .equ    COP_STATUS, 0x60007004
  46.     .equ    IIS_CONFIG, 0x70002800
  47.     .equ    SLEEP,    0x80000000
  48.     .equ    WAKE,     0x0
  49.     .equ    SLEEPING, 0x80000000
  50.     .equ    CACHE_CTRL, 0x6000c000
  51. #endif
  52.  
  53.     msr    cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */
  54.  
  55.     b      pad_skip
  56.  
  57. .space 60*4 /* For bootloader builds on targets with mi4 firmware, scramble
  58.                writes data to 0xe0-0xeb, so jump past that. For normal builds
  59.                this provides more than enough space for exception vectors */
  60.  
  61. pad_skip:
  62.  
  63. #ifdef BOOTLOADER
  64. /* 1 - Copy the bootloader to IRAM */
  65.     /* get the high part of our execute address */
  66.     and    r4, pc, #0xffff0000
  67.  
  68.     /* Copy bootloader to safe area - 0x40000000 */
  69.     mov    r5, #0x40000000
  70.     ldr    r6, = _dataend
  71. 1:
  72.     cmp    r5, r6
  73.     ldrcc  r2, [r4], #4
  74.     strcc  r2, [r5], #4
  75.     bcc    1b
  76.  
  77. /* 2 - Jump both CPU and COP there */
  78.     ldr    pc, =start_loc    /* jump to the relocated start_loc:  */
  79.  
  80. start_loc:
  81.  
  82. #else /* BOOTLOADER */
  83. #ifdef SANSA_E200
  84.     /* On the Sansa, copying the vectors fails if the cache is initialised */
  85.     ldr    r1, =CACHE_CTRL
  86.     mov    r2, #0x0
  87.     str    r2, [r1]
  88. #endif
  89.     /* We need to remap memory from wherever SDRAM is mapped natively, to
  90.        base address 0, so we can put our exception vectors there. We don't
  91.        want to do this remapping while executing from SDRAM, so we copy the
  92.        remapping code to IRAM, then execute from there. Hence, the following
  93.        code is compiled for address 0, but is currently executing at either
  94.        0x28000000 or 0x10000000, depending on chipset version. Do not use any
  95.        absolute addresses until remapping has been done. */
  96.     ldr    r1, =0x40000000
  97.     ldr    r2, =remap_start
  98.     ldr    r3, =remap_end
  99.  
  100.     and    r5, pc, #0xff000000 /* adjust for execute address */
  101.     orr    r2, r2, r5
  102.     orr    r3, r3, r5
  103.  
  104.     /* copy the code to 0x40000000 */
  105. 1:
  106.     ldr    r4, [r2], #4
  107.     str    r4, [r1], #4
  108.     cmp    r2, r3
  109.     ble    1b
  110.  
  111.     ldr    r3, =0x3f84     /* r3 and r1 values here are magic, don't touch */
  112.     orr    r3, r3, r5      /* adjust for execute address */
  113.     ldr    r2, =0xf000f014
  114.     mov    r1, #0x3a00
  115.     ldr    r0, =0xf000f010
  116.     mov    pc, #0x40000000
  117.  
  118. remap_start:
  119.     str    r1, [r0]
  120.     str    r3, [r2]
  121.     ldr    r0, L_post_remap
  122.     mov    pc, r0
  123. L_post_remap: .word remap_end
  124. remap_end:
  125.  
  126. #endif
  127.  
  128.     /* Find out which processor we are */
  129.     ldr    r0, =PROC_ID
  130.     ldr    r0, [r0]
  131.     and    r0, r0, #0xff
  132.     cmp    r0, #0x55
  133.     beq    cpu
  134.    
  135.     /* put us (co-processor) to sleep */
  136.     ldr    r4, =COP_CTRL
  137.     mov    r3, #SLEEP
  138.     str    r3, [r4]
  139.     ldr    pc, =cop_wake_start
  140.  
  141. cop_wake_start:
  142.     /* COP: Invalidate cache */
  143.     ldr    r0, =0xf000f044
  144.     ldr    r1, [r0]
  145.     orr    r1, r1, #0x6
  146.     str    r1, [r0]
  147.  
  148.     ldr    r0, =0x6000c000
  149. 1:
  150.     ldr    r1, [r0]
  151.     tst    r1, #0x8000
  152.     bne    1b
  153.    
  154. #ifdef BOOTLOADER
  155.     ldr    r0, =startup_loc
  156.     ldr    pc, [r0]
  157. #else
  158.     /* Setup stack for COP */
  159.     ldr    sp, =cop_stackend
  160.     mov    r3, sp
  161.     ldr    r2, =cop_stackbegin
  162.     ldr    r4, =0xdeadbeef
  163. 2:
  164.     cmp    r3, r2
  165.     strhi  r4, [r2], #4
  166.     bhi    2b
  167.  
  168.     ldr    sp, =cop_stackend
  169.    
  170.     /* Run cop_main() in apps/main.c */
  171.     bl     cop_main
  172. #endif
  173.  
  174. cpu:
  175.     /* Wait for COP to be sleeping */
  176.     ldr    r4, =COP_STATUS
  177. 1:
  178.     ldr    r3, [r4]
  179.     ands   r3, r3, #SLEEPING
  180.     beq    1b
  181.    
  182. #ifndef BOOTLOADER
  183.     /* Copy exception handler code to address 0 */
  184.     ldr    r2, =_vectorsstart
  185.     ldr    r3, =_vectorsend
  186.     ldr    r4, =_vectorscopy
  187. 1:
  188.     cmp    r3, r2
  189.     ldrhi  r5, [r4], #4
  190.     strhi  r5, [r2], #4
  191.     bhi    1b
  192. #endif
  193.  
  194.     /* Initialise bss section to zero */
  195.     ldr    r2, =_edata
  196.     ldr    r3, =_end
  197.     mov    r4, #0
  198. 1:
  199.     cmp    r3, r2
  200.     strhi  r4, [r2], #4
  201.     bhi    1b
  202.        
  203. #ifndef BOOTLOADER
  204.     /* Copy the IRAM */
  205.     ldr    r2, =_iramcopy
  206.     ldr    r3, =_iramstart
  207.     ldr    r4, =_iramend
  208. 1:
  209.     cmp    r4, r3
  210.     ldrhi  r5, [r2], #4
  211.     strhi  r5, [r3], #4
  212.     bhi    1b
  213. #endif
  214.  
  215.     /* Set up some stack and munge it with 0xdeadbeef */
  216.     ldr    sp, =stackend
  217.     mov    r3, sp
  218.     ldr    r2, =stackbegin
  219.     ldr    r4, =0xdeadbeef
  220. 1:
  221.     cmp    r3, r2
  222.     strhi  r4, [r2], #4
  223.     bhi    1b
  224.  
  225. #ifdef BOOTLOADER
  226.  
  227.     /* execute the loader - this will load an image to 0x10000000 */
  228.     bl     main
  229.  
  230.     ldr    r1, =startup_loc
  231.     str    r0, [r1]
  232.  
  233.     /* Flush cache */
  234.     ldr    r3, =0xf000f044
  235.     ldr    r4, [r3]
  236.     orr    r4, r4, #0x2
  237.     str    r4, [r3]
  238.  
  239.     ldr    r3, =0x6000c000
  240. 1:
  241.     ldr    r4, [r3]
  242.     tst    r4, #0x8000
  243.     bne    1b
  244.  
  245.     /* Wake up the coprocessor before executing the firmware */
  246.     ldr    r4, =COP_CTRL
  247.     mov    r3, #WAKE
  248.     str    r3, [r4]
  249.  
  250.     mov    pc, r0
  251.  
  252. startup_loc:
  253.     .word    0x0
  254.  
  255. .align 8    /* starts at 0x100 */
  256. .global boot_table
  257. boot_table:
  258.     /* here comes the boot table, don't move its offset */
  259.     .space 400
  260.  
  261. #else /* BOOTLOADER */
  262.  
  263.     /* Set up stack for IRQ mode */
  264.     msr    cpsr_c, #0xd2
  265.     ldr    sp, =irq_stack
  266.     /* Set up stack for FIQ mode */
  267.     msr    cpsr_c, #0xd1
  268.     ldr    sp, =fiq_stack
  269.     /* We'll load the banked FIQ mode registers with useful values here.
  270.        These values will be used in the FIQ handler in pcm_playback.c */
  271.     ldr    r12, =IIS_CONFIG
  272.  
  273.     ldr    r11, =p
  274.  
  275.     /* Let abort and undefined modes use IRQ stack */
  276.     msr    cpsr_c, #0xd7
  277.     ldr    sp, =irq_stack
  278.     msr    cpsr_c, #0xdb
  279.     ldr    sp, =irq_stack
  280.     /* Switch to supervisor mode */
  281.     msr    cpsr_c, #0xd3
  282.     ldr    sp, =stackend
  283.     bl     main
  284.     /* main() should never return */
  285.    
  286. /* Exception handlers. Will be copied to address 0 after memory remapping */
  287.     .section .vectors,"aw"
  288.     ldr    pc, [pc, #24]
  289.     ldr    pc, [pc, #24]
  290.     ldr    pc, [pc, #24]
  291.     ldr    pc, [pc, #24]
  292.     ldr    pc, [pc, #24]
  293.     ldr    pc, [pc, #24]
  294.     ldr    pc, [pc, #24]
  295.     ldr    pc, [pc, #24]
  296.  
  297.     /* Exception vectors */
  298.     .global vectors
  299. vectors:
  300.     .word  start
  301.     .word  undef_instr_handler
  302.     .word  software_int_handler
  303.     .word  prefetch_abort_handler
  304.     .word  data_abort_handler
  305.     .word  reserved_handler
  306.     .word  irq_handler
  307.     .word  fiq_handler
  308.  
  309.     .text
  310.  
  311. #ifndef STUB
  312.     .global irq
  313.     .global fiq
  314.     .global UIE
  315. #endif
  316.  
  317. /* All illegal exceptions call into UIE with exception address as first
  318.    parameter. This is calculated differently depending on which exception
  319.    we're in. Second parameter is exception number, used for a string lookup
  320.    in UIE.
  321.  */
  322. undef_instr_handler:
  323.     mov    r0, lr
  324.     mov    r1, #0
  325.     b      UIE
  326.  
  327. /* We run supervisor mode most of the time, and should never see a software
  328.    exception being thrown. Perhaps make it illegal and call UIE?
  329.  */
  330. software_int_handler:
  331. reserved_handler:
  332.     movs   pc, lr
  333.  
  334. prefetch_abort_handler:
  335.     sub    r0, lr, #4
  336.     mov    r1, #1
  337.     b      UIE
  338.  
  339. fiq_handler:
  340.     @ Branch straight to FIQ handler in pcm_playback.c. This also handles the
  341.     @ the correct return sequence.
  342.     ldr    pc, =fiq
  343.  
  344. data_abort_handler:
  345.     sub    r0, lr, #8
  346.     mov    r1, #2
  347.     b      UIE
  348.  
  349. irq_handler:
  350. #ifndef STUB
  351.     stmfd  sp!, {r0-r3, r12, lr}
  352.     bl     irq
  353.     ldmfd  sp!, {r0-r3, r12, lr}
  354. #endif
  355.     subs   pc, lr, #4
  356.  
  357. #ifdef STUB
  358. UIE:
  359.     b UIE
  360. #endif
  361.  
  362. /* 256 words of IRQ stack */
  363.     .space 256*4
  364. irq_stack:
  365.  
  366. /* 256 words of FIQ stack */
  367.     .space 256*4
  368. fiq_stack:
  369. #endif /* BOOTLOADER */

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