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Miscellany
Tuesday, December 5th, 2006 at 5:20:13pm UTC 

  1. /***************************************************************************
  2.  *             __________               __   ___.
  3.  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
  4.  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
  5.  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
  6.  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  7.  *                     \/            \/     \/    \/            \/
  8.  * $Id: crt0-pp.S,v 1.2 2006-11-22 00:49:16 dan_a Exp $
  9.  *
  10.  * Copyright (C) 2002 by Linus Nielsen Feltzing
  11.  *
  12.  * All files in this archive are subject to the GNU General Public License.
  13.  * See the file COPYING in the source tree root for full license agreement.
  14.  *
  15.  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16.  * KIND, either express or implied.
  17.  *
  18.  ****************************************************************************/
  19. #include "config.h"
  20. #include "cpu.h"
  21.  
  22.     .section .init.text,"ax",%progbits
  23.  
  24.     .global    start
  25. start:
  26.  
  27. /* PortalPlayer bootloader and startup code based on startup.s from the iPodLinux
  28.  * loader
  29.  *
  30.  * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
  31.  * Copyright (c) 2005, Bernard Leach <[email protected]>
  32.  *
  33.  */
  34. #if CONFIG_CPU == PP5002
  35.     .equ    PROC_ID,  0xc4000000
  36.     .equ    COP_CTRL, 0xcf004058
  37.     .equ    COP_STATUS, 0xcf004050
  38.     .equ    IIS_CONFIG, 0xc0002500
  39.     .equ    SLEEP,    0xca
  40.     .equ    WAKE,     0xce
  41.     .equ    SLEEPING, 0x4000
  42. #else
  43.     .equ    PROC_ID,  0x60000000
  44.     .equ    COP_CTRL, 0x60007004
  45.     .equ    COP_STATUS, 0x60007004
  46.     .equ    IIS_CONFIG, 0x70002800
  47.     .equ    SLEEP,    0x80000000
  48.     .equ    WAKE,     0x0
  49.     .equ    SLEEPING, 0x80000000
  50.     .equ    CACHE_CTRL, 0x6000c000
  51. #endif
  52.  
  53.     msr    cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */
  54.  
  55. /* MI4Code writes data to 0xe0-0xeb so jump past that */
  56.     b      pad_skip
  57.  
  58. .space 60*4
  59.  
  60. pad_skip
  61. /* 1 - Copy the bootloader to IRAM */
  62.     /* get the high part of our execute address */
  63.     and    r4, pc, #0xff000000
  64.  
  65.     /* Copy bootloader to safe area - 0x40000000 */
  66.     mov    r5, #0x40000000
  67.     ldr    r6, = _dataend
  68.     sub    r0, r6, r5       /* length of loader */
  69.     add    r8, r4, r0       /* r8 points to start of loader */
  70. 1:
  71.     cmp    r5, r6
  72.     ldrcc  r2, [r4], #4
  73.     strcc  r2, [r5], #4
  74.     bcc    1b
  75.  
  76. /* 2 - Jump both CPU and COP there */
  77.     ldr    pc, =start_loc    /* jump to the relocated start_loc:  */
  78.  
  79. start_loc:
  80.  
  81.     /* Find out which processor we are */
  82.     mov    r0, #PROC_ID
  83.     ldr    r0, [r0]
  84.     and    r0, r0, #0xff
  85.     cmp    r0, #0x55
  86.     beq    cpu
  87.  
  88.     /* put us (co-processor) to sleep */
  89.     ldr    r4, =COP_CTRL
  90.     mov    r3, #SLEEP
  91.     str    r3, [r4]
  92.     ldr    pc, =cop_wake_start
  93.  
  94. cop_wake_start:
  95.     /* COP: Invalidate cache */
  96.     ldr    r0, =0xf000f044
  97.     ldr    r1, [r0]
  98.     orr    r1, r1, #0x6
  99.     str    r1, [r0]
  100.  
  101.     ldr    r0, =0x6000c000
  102. 1:
  103.     ldr    r1, [r0]
  104.     tst    r1, #0x8000
  105.     bne    1b
  106.  
  107.     ldr    r0, =startup_loc
  108.     ldr    pc, [r0]
  109.  
  110. cpu:
  111.     /* Wait for COP to be sleeping */
  112.     ldr    r4, =COP_STATUS
  113. 1:
  114.     ldr    r3, [r4]
  115.     ands   r3, r3, #SLEEPING
  116.     beq    1b
  117.  
  118.     /* Initialise bss section to zero */
  119.     ldr    r2, =_edata
  120.     ldr    r3, =_end
  121.     mov    r4, #0
  122. 1:
  123.     cmp    r3, r2
  124.     strhi  r4, [r2], #4
  125.     bhi    1b
  126.  
  127.     /* Set up some stack and munge it with 0xdeadbeef */
  128.     ldr    sp, =stackend
  129.     mov    r3, sp
  130.     ldr    r2, =stackbegin
  131.     ldr    r4, =0xdeadbeef
  132. 1:
  133.     cmp    r3, r2
  134.     strhi  r4, [r2], #4
  135.     bhi    1b
  136.  
  137.     mov    r0, r8 /* r8 holds the start of the loader - copy this to r0 */
  138.  
  139.     /* execute the loader - this will load an image to 0x10000000 */
  140.     bl     main
  141.  
  142.     ldr    r1, =startup_loc
  143.     str    r0, [r1]
  144.  
  145.     /* Flush cache */
  146.     ldr    r3, =0xf000f044
  147.     ldr    r4, [r3]
  148.     orr    r4, r4, #0x2
  149.     str    r4, [r3]
  150.  
  151.     ldr    r3, =0x6000c000
  152. 1:
  153.     ldr    r4, [r3]
  154.     tst    r4, #0x8000
  155.     bne    1b
  156.  
  157.     /* Wake up the coprocessor before executing the firmware */
  158.     ldr    r4, =COP_CTRL
  159.     mov    r3, #WAKE
  160.     str    r3, [r4]
  161.  
  162.     mov    pc, r0
  163.  
  164. startup_loc:
  165.     .word    0x0
  166.  
  167. .align 8    /* starts at 0x100 */
  168. .global boot_table
  169. boot_table:
  170.     /* here comes the boot table, don't move its offset */
  171.     .space 400

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