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Miscellany
Monday, December 4th, 2006 at 2:54:09pm UTC 

  1. /***************************************************************************
  2.  *             __________               __   ___.
  3.  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
  4.  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
  5.  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
  6.  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  7.  *                     \/            \/     \/    \/            \/
  8.  * $Id: crt0-pp.S,v 1.2 2006/11/22 00:49:16 dan_a Exp $
  9.  *
  10.  * Copyright (C) 2002 by Linus Nielsen Feltzing
  11.  *
  12.  * All files in this archive are subject to the GNU General Public License.
  13.  * See the file COPYING in the source tree root for full license agreement.
  14.  *
  15.  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16.  * KIND, either express or implied.
  17.  *
  18.  ****************************************************************************/
  19. #include "config.h"
  20. #include "cpu.h"
  21.  
  22.     .section .init.text,"ax",%progbits
  23.  
  24.     .global    start
  25. start:
  26.  
  27. /* PortalPlayer bootloader and startup code based on startup.s from the iPodLinux
  28.  * loader
  29.  *
  30.  * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
  31.  * Copyright (c) 2005, Bernard Leach <[email protected]>
  32.  *
  33.  */
  34. #if CONFIG_CPU == PP5002
  35.     .equ    PROC_ID,  0xc4000000
  36.     .equ    COP_CTRL, 0xcf004058
  37.     .equ    COP_STATUS, 0xcf004050
  38.     .equ    IIS_CONFIG, 0xc0002500
  39.     .equ    SLEEP,    0xca
  40.     .equ    WAKE,     0xce
  41.     .equ    SLEEPING, 0x4000
  42. #else
  43.     .equ    PROC_ID,  0x60000000
  44.     .equ    COP_CTRL, 0x60007004
  45.     .equ    COP_STATUS, 0x60007004
  46.     .equ    IIS_CONFIG, 0x70002800
  47.     .equ    SLEEP,    0x80000000
  48.     .equ    WAKE,     0x0
  49.     .equ    SLEEPING, 0x80000000
  50.     .equ    CACHE_CTRL, 0x6000c000
  51. #endif
  52.  
  53.     msr    cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */
  54.  
  55.     b      pad_skip
  56.  
  57. .space 50*4
  58.  
  59. pad_skip:
  60. #ifdef SANSA_E200
  61.     /* On the Sansa, copying the vectors fails if the cache is initialised */
  62.     ldr    r1, =CACHE_CTRL
  63.     mov    r2, #0x0
  64.     str    r2, [r1]
  65. #endif
  66.     /* We need to remap memory from wherever SDRAM is mapped natively, to
  67.        base address 0, so we can put our exception vectors there. We don't
  68.        want to do this remapping while executing from SDRAM, so we copy the
  69.        remapping code to IRAM, then execute from there. Hence, the following
  70.        code is compiled for address 0, but is currently executing at either
  71.        0x28000000 or 0x10000000, depending on chipset version. Do not use any
  72.        absolute addresses until remapping has been done. */
  73.     ldr    r1, =0x40000000
  74.     ldr    r2, =remap_start
  75.     ldr    r3, =remap_end
  76.  
  77.     and    r5, pc, #0xff000000 /* adjust for execute address */
  78.     orr    r2, r2, r5
  79.     orr    r3, r3, r5
  80.  
  81.     /* copy the code to 0x40000000 */
  82. 1:
  83.     ldr    r4, [r2], #4
  84.     str    r4, [r1], #4
  85.     cmp    r2, r3
  86.     ble    1b
  87.  
  88.     ldr    r3, =0x3f84     /* r3 and r1 values here are magic, don't touch */
  89.     orr    r3, r3, r5      /* adjust for execute address */
  90.     ldr    r2, =0xf000f014
  91.     mov    r1, #0x3a00
  92.     ldr    r0, =0xf000f010
  93.     mov    pc, #0x40000000
  94.  
  95. remap_start:
  96.     str    r1, [r0]
  97.     str    r3, [r2]
  98.     ldr    r0, L_post_remap
  99.     mov    pc, r0
  100. L_post_remap: .word remap_end
  101. remap_end:
  102.  
  103.     /* After doing the remapping, send the COP to sleep.
  104.        On wakeup it will go to cop_init */
  105.     ldr    r0, =PROC_ID
  106.     ldr    r0, [r0]
  107.     and    r0, r0, #0xff
  108.     cmp    r0, #0x55
  109.     beq    cpu
  110.    
  111.     /* put us (co-processor) to sleep */
  112.     ldr    r4, =COP_CTRL
  113.     mov    r3, #SLEEP
  114.     str    r3, [r4]
  115.     ldr    pc, =cop_wake_start
  116.  
  117. cop_wake_start:
  118.     /* COP: Invalidate cache */
  119.     ldr    r0, =0xf000f044
  120.     ldr    r1, [r0]
  121.     orr    r1, r1, #0x6
  122.     str    r1, [r0]
  123.  
  124.     ldr    r0, =0x6000c000
  125. 1:
  126.     ldr    r1, [r0]
  127.     tst    r1, #0x8000
  128.     bne    1b
  129.    
  130.     ldr    sp, =cop_stackend
  131.     mov    r3, sp
  132.     ldr    r2, =cop_stackbegin
  133.     ldr    r4, =0xdeadbeef
  134. 2:
  135.     cmp    r3, r2
  136.     strhi  r4, [r2], #4
  137.     bhi    2b
  138.  
  139.     ldr    sp, =cop_stackend
  140.     bl     cop_main
  141.  
  142. cpu:
  143.     /* Wait for COP to be sleeping */
  144.     ldr    r4, =COP_STATUS
  145. 1:
  146.     ldr    r3, [r4]
  147.     ands   r3, r3, #SLEEPING
  148.     beq    1b
  149.    
  150. #ifndef DEBUG
  151.     /* Copy exception handler code to address 0 */
  152.     ldr    r2, =_vectorsstart
  153.     ldr    r3, =_vectorsend
  154.     ldr    r4, =_vectorscopy
  155. 1:
  156.     cmp    r3, r2
  157.     ldrhi  r5, [r4], #4
  158.     strhi  r5, [r2], #4
  159.     bhi    1b
  160. #else
  161.     ldr    r1, =vectors
  162.     ldr    r0, =irq_handler
  163.     str    r0, [r1, #24]
  164.     ldr    r0, =fiq_handler
  165.     str    r0, [r1, #28]
  166. #endif
  167.  
  168. #ifndef STUB
  169.     /* Zero out IBSS */
  170.     ldr    r2, =_iedata
  171.     ldr    r3, =_iend
  172.     mov    r4, #0
  173. 1:
  174.     cmp    r3, r2
  175.     strhi  r4, [r2], #4
  176.     bhi    1b
  177.  
  178.     /* Copy the IRAM */
  179.     ldr    r2, =_iramcopy
  180.     ldr    r3, =_iramstart
  181.     ldr    r4, =_iramend
  182. 1:
  183.     cmp    r4, r3
  184.     ldrhi  r5, [r2], #4
  185.     strhi  r5, [r3], #4
  186.     bhi    1b
  187. #endif /* !STUB */
  188.  
  189.     /* Initialise bss section to zero */
  190.     ldr    r2, =_edata
  191.     ldr    r3, =_end
  192.     mov    r4, #0
  193. 1:
  194.     cmp    r3, r2
  195.     strhi  r4, [r2], #4
  196.     bhi    1b
  197.    
  198.     /* Set up some stack and munge it with 0xdeadbeef */
  199.     ldr    sp, =stackend
  200.     mov    r3, sp
  201.     ldr    r2, =stackbegin
  202.     ldr    r4, =0xdeadbeef
  203. 1:
  204.     cmp    r3, r2
  205.     strhi  r4, [r2], #4
  206.     bhi    1b
  207.  
  208.  
  209.     /* Set up stack for IRQ mode */
  210.     msr    cpsr_c, #0xd2
  211.     ldr    sp, =irq_stack
  212.     /* Set up stack for FIQ mode */
  213.     msr    cpsr_c, #0xd1
  214.     ldr    sp, =fiq_stack
  215.     /* We'll load the banked FIQ mode registers with useful values here.
  216.        These values will be used in the FIQ handler in pcm_playback.c */
  217.     ldr    r12, =IIS_CONFIG
  218.  
  219.     ldr    r11, =p
  220.  
  221.     /* Let abort and undefined modes use IRQ stack */
  222.     msr    cpsr_c, #0xd7
  223.     ldr    sp, =irq_stack
  224.     msr    cpsr_c, #0xdb
  225.     ldr    sp, =irq_stack
  226.     /* Switch to supervisor mode */
  227.     msr    cpsr_c, #0xd3
  228.     ldr    sp, =stackend
  229.     bl     main
  230.     /* main() should never return */
  231.    
  232. /* Exception handlers. Will be copied to address 0 after memory remapping */
  233.     .section .vectors,"aw"
  234.     ldr    pc, [pc, #24]
  235.     ldr    pc, [pc, #24]
  236.     ldr    pc, [pc, #24]
  237.     ldr    pc, [pc, #24]
  238.     ldr    pc, [pc, #24]
  239.     ldr    pc, [pc, #24]
  240.     ldr    pc, [pc, #24]
  241.     ldr    pc, [pc, #24]
  242.  
  243.     /* Exception vectors */
  244.     .global vectors
  245. vectors:
  246.     .word  start
  247.     .word  undef_instr_handler
  248.     .word  software_int_handler
  249.     .word  prefetch_abort_handler
  250.     .word  data_abort_handler
  251.     .word  reserved_handler
  252.     .word  irq_handler
  253.     .word  fiq_handler
  254.  
  255.     .text
  256.  
  257. #ifndef STUB
  258.     .global irq
  259.     .global fiq
  260.     .global UIE
  261. #endif
  262.  
  263. /* All illegal exceptions call into UIE with exception address as first
  264.    parameter. This is calculated differently depending on which exception
  265.    we're in. Second parameter is exception number, used for a string lookup
  266.    in UIE.
  267.  */
  268. undef_instr_handler:
  269.     mov    r0, lr
  270.     mov    r1, #0
  271.     b      UIE
  272.  
  273. /* We run supervisor mode most of the time, and should never see a software
  274.    exception being thrown. Perhaps make it illegal and call UIE?
  275.  */
  276. software_int_handler:
  277. reserved_handler:
  278.     movs   pc, lr
  279.  
  280. prefetch_abort_handler:
  281.     sub    r0, lr, #4
  282.     mov    r1, #1
  283.     b      UIE
  284.  
  285. fiq_handler:
  286.     @ Branch straight to FIQ handler in pcm_playback.c. This also handles the
  287.     @ the correct return sequence.
  288.     ldr    pc, =fiq
  289.  
  290. data_abort_handler:
  291.     sub    r0, lr, #8
  292.     mov    r1, #2
  293.     b      UIE
  294.  
  295. irq_handler:
  296. #ifndef STUB
  297.     stmfd  sp!, {r0-r3, r12, lr}
  298.     bl     irq
  299.     ldmfd  sp!, {r0-r3, r12, lr}
  300. #endif
  301.     subs   pc, lr, #4
  302.  
  303. #ifdef STUB
  304. UIE:
  305.     b UIE
  306. #endif
  307.  
  308. /* 256 words of IRQ stack */
  309.     .space 256*4
  310. irq_stack:
  311.  
  312. /* 256 words of FIQ stack */
  313.     .space 256*4
  314. fiq_stack:

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