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Miscellany
Monday, December 4th, 2006 at 1:50:52pm UTC 

  1. /***************************************************************************
  2.  *             __________               __   ___.
  3.  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
  4.  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
  5.  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
  6.  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  7.  *                     \/            \/     \/    \/            \/
  8.  * $Id: crt0-pp.S,v 1.2 2006-11-22 00:49:16 dan_a Exp $
  9.  *
  10.  * Copyright (C) 2002 by Linus Nielsen Feltzing
  11.  *
  12.  * All files in this archive are subject to the GNU General Public License.
  13.  * See the file COPYING in the source tree root for full license agreement.
  14.  *
  15.  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16.  * KIND, either express or implied.
  17.  *
  18.  ****************************************************************************/
  19. #include "config.h"
  20. #include "cpu.h"
  21.  
  22.     .section .init.text,"ax",%progbits
  23.  
  24.     .global    start
  25. start:
  26.  
  27. /* PortalPlayer bootloader and startup code based on startup.s from the iPodLinux
  28.  * loader
  29.  *
  30.  * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
  31.  * Copyright (c) 2005, Bernard Leach <[email protected]>
  32.  *
  33.  */
  34.     .equ    PROC_ID,  0x60000000
  35.     .equ    COP_CTRL, 0x60007004
  36.     .equ    COP_STATUS, 0x60007004
  37.     .equ    IIS_CONFIG, 0x70002800
  38.     .equ    SLEEP,    0x80000000
  39.     .equ    WAKE,     0x0
  40.     .equ    SLEEPING, 0x80000000
  41.     .equ    CACHE_CTRL, 0x6000c000
  42.  
  43.     msr    cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */
  44.  
  45. /* 1 - Copy the bootloader to IRAM */
  46.     /* get the high part of our execute address */
  47.     and    r4, pc, #0xff000000
  48.  
  49.     /* Copy bootloader to safe area - 0x40000000 */
  50.     mov    r5, #0x40000000
  51.     ldr    r6, = _dataend
  52.     sub    r0, r6, r5       /* length of loader */
  53.     add    r8, r4, r0       /* r8 points to start of loader */
  54. 1:
  55.     cmp    r5, r6
  56.     ldrcc  r2, [r4], #4
  57.     strcc  r2, [r5], #4
  58.     bcc    1b
  59.  
  60. /* 2 - Jump both CPU and COP there */
  61.     ldr    pc, =start_loc    /* jump to the relocated start_loc:  */
  62.  
  63. start_loc:
  64.  
  65.     /* Find out which processor we are */
  66.     mov    r0, #PROC_ID
  67.     ldr    r0, [r0]
  68.     and    r0, r0, #0xff
  69.     cmp    r0, #0x55
  70.     beq    cpu
  71.  
  72.     /* put us (co-processor) to sleep */
  73.     ldr    r4, =COP_CTRL
  74.     mov    r3, #SLEEP
  75.     str    r3, [r4]
  76.     ldr    pc, =cop_wake_start
  77.  
  78. cop_wake_start:
  79.     /* COP: Invalidate cache */
  80.     ldr    r0, =0xf000f044
  81.     ldr    r1, [r0]
  82.     orr    r1, r1, #0x6
  83.     str    r1, [r0]
  84.  
  85.  
  86.     ldr    r0, =0x6000c000
  87. 1:
  88.     ldr    r1, [r0]
  89.     tst    r1, #0x8000
  90.     bne    1b
  91.  
  92.     ldr    r0, =startup_loc
  93.     ldr    pc, [r0]
  94.  
  95. cpu:
  96.     /* Wait for COP to be sleeping */
  97.     ldr    r4, =COP_STATUS
  98. 1:
  99.     ldr    r3, [r4]
  100.     ands   r3, r3, #SLEEPING
  101.     beq    1b
  102.  
  103.     /* Initialise bss section to zero */
  104.     ldr    r2, =_edata
  105.     ldr    r3, =_end
  106.     mov    r4, #0
  107. 1:
  108.     cmp    r3, r2
  109.     strhi  r4, [r2], #4
  110.     bhi    1b
  111.  
  112.     /* Set up some stack and munge it with 0xdeadbeef */
  113.     ldr    sp, =stackend
  114.     mov    r3, sp
  115.     ldr    r2, =stackbegin
  116.     ldr    r4, =0xdeadbeef
  117. 1:
  118.     cmp    r3, r2
  119.     strhi  r4, [r2], #4
  120.     bhi    1b
  121.  
  122.     mov    r0, r8 /* r8 holds the start of the loader - copy this to r0 */
  123.  
  124.     /* execute the loader - this will load an image to 0x10000000 */
  125.     bl     main
  126.  
  127.     ldr    r1, =startup_loc
  128.     str    r0, [r1]
  129.     b      1f
  130. /* MI4Code writes data here! */
  131. .space  10*4
  132. 1:
  133.     /* Flush cache */
  134.     ldr    r3, =0xf000f044
  135.     ldr    r4, [r3]
  136.     orr    r4, r4, #0x2
  137.     str    r4, [r3]
  138.  
  139.     ldr    r3, =0x6000c000
  140. 1:
  141.     ldr    r4, [r3]
  142.     tst    r4, #0x8000
  143.     bne    1b
  144.  
  145.     /* Wake up the coprocessor before executing the firmware */
  146.     ldr    r4, =COP_CTRL
  147.     mov    r3, #WAKE
  148.     str    r3, [r4]
  149.  
  150.     mov    pc, r0
  151.  
  152. startup_loc:
  153.     .word    0x0
  154.  
  155. .align 8    /* starts at 0x100 */
  156. .global boot_table
  157. boot_table:
  158.     /* here comes the boot table, don't move its offset */
  159.     .space 400

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