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Saturday, April 13th, 2013 at 2:26:13pm UTC 

  1. Running DRC.
  2. ERROR:PhysDesignRules:368 - The signal <mmc_dat<0>_OBUF> is incomplete. The
  3.    signal is not driven by any source pin in the design.
  4. ERROR:PhysDesignRules:368 - The signal <mmc_dat<2>_OBUF> is incomplete. The
  5.    signal is not driven by any source pin in the design.
  6. ERROR:PhysDesignRules:368 - The signal <mmc_dat<3>_OBUF> is incomplete. The
  7.    signal is not driven by any source pin in the design.
  8. WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
  9.    (RAMB8BWER).  9K Block RAM initialization data, both user defined and
  10.    default, may be incorrect and should not be used.  For more information,
  11.    please reference Xilinx Answer Record 39999.
  12. ERROR:PhysDesignRules:10 - The network <mmc_dat<0>_OBUF> is completely unrouted.
  13. ERROR:PhysDesignRules:10 - The network <mmc_dat<2>_OBUF> is completely unrouted.
  14. ERROR:PhysDesignRules:10 - The network <mmc_dat<3>_OBUF> is completely unrouted.
  15. ERROR:Bitgen:25 - DRC detected 6 errors and 1 warnings.  Please see the
  16.    previously displayed individual error or warning messages for more details.
  17. INFO:Bitgen:328 - DRC errors can be caused by a missing constraints file (.pcf).

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