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Untitled
Wednesday, October 25th, 2006 at 1:35:47am UTC 

  1. diff --git a/apps/main.c b/apps/main.c
  2. index fdc5c0f..50c77f7 100644
  3. --- a/apps/main.c
  4. +++ b/apps/main.c
  5. @@ -271,6 +271,9 @@ #if defined(CONFIG_CHARGING) && (CONFIG_
  6.      /* if nobody initialized ATA before, I consider this a cold start */
  7.      bool coldstart = (PACR2 & 0x4000) != 0; /* starting from Flash */
  8.  #endif
  9. +#ifdef CPU_PP
  10. +    COP_CTL = PROC_WAKE;
  11. +#endif
  12.      system_init();
  13.      kernel_init();
  14.  
  15. @@ -511,9 +514,14 @@ void cop_main(void)
  16.     so it should not be assumed that the coprocessor be usable even on
  17.     platforms which support it.
  18.  
  19. -   At present all we do is send the COP to sleep if anything wakes it. */
  20. +   A kernel thread runs on the coprocessor, which just waits for other
  21. +   threads to be added */
  22. +
  23. +    system_init();
  24. +    kernel_init();
  25. +
  26.      while(1) {
  27. -        COP_CTL = PROC_SLEEP;
  28. +        sleep(HZ);
  29.      }
  30.  }
  31.  #endif
  32. diff --git a/apps/playback.c b/apps/playback.c
  33. index 370c7e4..c7200f6 100644
  34. --- a/apps/playback.c
  35. +++ b/apps/playback.c
  36. @@ -173,12 +173,12 @@ #endif
  37.  
  38.  
  39.  
  40. -static struct mutex mutex_codecthread;
  41. -static struct event_queue codec_callback_queue;
  42. +static struct mutex mutex_codecthread IDATA_ATTR;
  43. +static struct event_queue codec_callback_queue IDATA_ATTR;
  44.  
  45. -static volatile bool audio_codec_loaded;
  46. -static volatile bool playing;
  47. -static volatile bool paused;
  48. +static volatile bool audio_codec_loaded IDATA_ATTR;
  49. +static volatile bool playing IDATA_ATTR;
  50. +static volatile bool paused IDATA_ATTR;
  51.  
  52.  /* Is file buffer currently being refilled? */
  53.  static volatile bool filling IDATA_ATTR;
  54. @@ -268,7 +268,7 @@ static void audio_reset_buffer(void);
  55.  
  56.  /* Codec thread */
  57.  extern struct codec_api ci;
  58. -static struct event_queue codec_queue;
  59. +static struct event_queue codec_queue IDATA_ATTR;
  60.  static long codec_stack[(DEFAULT_STACK_SIZE + 0x2000)/sizeof(long)]
  61.  IBSS_ATTR;
  62.  static const char codec_thread_name[] = "codec";
  63. @@ -280,14 +280,14 @@ #ifdef PLAYBACK_VOICE
  64.  extern struct codec_api ci_voice;
  65.  
  66.  static volatile bool voice_thread_start;
  67. -static volatile bool voice_is_playing;
  68. -static volatile bool voice_codec_loaded;
  69. +static volatile bool voice_is_playing IDATA_ATTR;
  70. +static volatile bool voice_codec_loaded IDATA_ATTR;
  71.  static void (*voice_getmore)(unsigned char** start, int* size);
  72.  static char *voicebuf;
  73.  static size_t voice_remaining;
  74.  static struct thread_entry *voice_thread_p = NULL;
  75.  
  76. -static struct event_queue voice_queue;
  77. +static struct event_queue voice_queue IDATA_ATTR;
  78.  static long voice_stack[(DEFAULT_STACK_SIZE + 0x2000)/sizeof(long)]
  79.  IBSS_ATTR;
  80.  static const char voice_thread_name[] = "voice codec";
  81. diff --git a/firmware/export/config.h b/firmware/export/config.h
  82. index 091de05..e5d681c 100644
  83. --- a/firmware/export/config.h
  84. +++ b/firmware/export/config.h
  85. @@ -234,14 +234,8 @@ #if (CONFIG_CPU == PP5002) || (CONFIG_CP
  86.  #define CPU_PP
  87.  
  88.  /* PP family has dual cores */
  89. -#if 0
  90. -/* Keep it as single core until dual core support is ready */
  91.  #define NUM_CORES 2
  92.  #define CURRENT_CORE current_core()
  93. -#endif
  94. -
  95. -#define NUM_CORES 1
  96. -#define CURRENT_CORE 0
  97.  #else
  98.  #define NUM_CORES 1
  99.  #define CURRENT_CORE 0
  100. diff --git a/firmware/export/pp5002.h b/firmware/export/pp5002.h
  101. index 59056e1..998ab73 100644
  102. --- a/firmware/export/pp5002.h
  103. +++ b/firmware/export/pp5002.h
  104. @@ -62,6 +62,9 @@ #define DEV_EN (*(volatile unsigned long
  105.  #define CPU_INT_STAT     (*(volatile unsigned long*)(0xcf001000))
  106.  #define CPU_INT_EN       (*(volatile unsigned long*)(0xcf001024))
  107.  #define CPU_INT_CLR      (*(volatile unsigned long*)(0xcf001028))
  108. +#define COP_INT_STAT     (*(volatile unsigned long*)(0xcf001010)) /* A guess */
  109. +#define COP_INT_EN       (*(volatile unsigned long*)(0xcf001034))
  110. +#define COP_INT_CLR      (*(volatile unsigned long*)(0xcf001038))
  111.  
  112.  #define USB2D_IDENT         (*(volatile unsigned long*)(0xc5000000))
  113.  #define USB_STATUS          (*(volatile unsigned long*)(0xc50001a4))
  114. diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h
  115. index be997e9..8bc9f3d 100644
  116. --- a/firmware/export/pp5020.h
  117. +++ b/firmware/export/pp5020.h
  118. @@ -139,6 +139,12 @@ #define CPU_INT_EN       (*(volatile uns
  119.  #define CPU_HI_INT_EN    (*(volatile unsigned long*)(0x60004124))
  120.  #define CPU_INT_CLR      (*(volatile unsigned long*)(0x60004028))
  121.  #define CPU_HI_INT_CLR   (*(volatile unsigned long*)(0x60004128))
  122. +#define COP_INT_STAT     (*(volatile unsigned long*)(0x60004004)) /* Guessed */
  123. +#define COP_HI_INT_STAT  (*(volatile unsigned long*)(0x60004104)) /* From IPL*/
  124. +#define COP_INT_EN       (*(volatile unsigned long*)(0x60004034)) /* Guessed */
  125. +#define COP_HI_INT_EN    (*(volatile unsigned long*)(0x60004134)) /* From IPL*/
  126. +#define COP_INT_CLR      (*(volatile unsigned long*)(0x60004038)) /* Guessed */
  127. +#define COP_HI_INT_CLR   (*(volatile unsigned long*)(0x60004138)) /* From IPL*/
  128.        
  129.  #define TIMER1_IRQ   0
  130.  #define TIMER2_IRQ   1
  131. diff --git a/firmware/kernel.c b/firmware/kernel.c
  132. index 6415f71..395339e 100644
  133. --- a/firmware/kernel.c
  134. +++ b/firmware/kernel.c
  135. @@ -45,10 +45,13 @@ void kernel_init(void)
  136.      /* Init the threading API */
  137.      init_threads();
  138.      
  139. -    memset(tick_funcs, 0, sizeof(tick_funcs));
  140. +    if(CURRENT_CORE == CPU)
  141. +    {
  142. +        memset(tick_funcs, 0, sizeof(tick_funcs));
  143.  
  144. -    num_queues = 0;
  145. -    memset(all_queues, 0, sizeof(all_queues));
  146. +        num_queues = 0;
  147. +        memset(all_queues, 0, sizeof(all_queues));
  148. +    }
  149.  
  150.      tick_start(1000/HZ);
  151.  }
  152. @@ -366,28 +369,36 @@ void TIMER1(void)
  153.      int i;
  154.  
  155.      TIMER1_VAL; /* Read value to ack IRQ */
  156. -    /* Run through the list of tick tasks */
  157. -    for (i = 0;i < MAX_NUM_TICK_TASKS;i++)
  158. +    /* Run through the list of tick tasks (using main core) */
  159. +    if (CURRENT_CORE == CPU)
  160.      {
  161. -        if (tick_funcs[i])
  162. +        for (i = 0;i < MAX_NUM_TICK_TASKS;i++)
  163.          {
  164. -            tick_funcs[i]();
  165. +            if (tick_funcs[i])
  166. +            {
  167. +                tick_funcs[i]();
  168. +            }
  169.          }
  170. -    }
  171.  
  172. -    current_tick++;
  173. +        current_tick++;
  174. +    }
  175.  }
  176.  #endif
  177.  
  178.  void tick_start(unsigned int interval_in_ms)
  179.  {
  180.  #ifndef BOOTLOADER
  181. -    TIMER1_CFG = 0x0;
  182. -    TIMER1_VAL;
  183. -    /* enable timer */
  184. -    TIMER1_CFG = 0xc0000000 | (interval_in_ms*1000 - 1);
  185. -    /* unmask interrupt source */
  186. -    CPU_INT_EN = TIMER1_MASK;
  187. +    if(CURRENT_CORE == CPU)
  188. +    {
  189. +        TIMER1_CFG = 0x0;
  190. +        TIMER1_VAL;
  191. +        /* enable timer */
  192. +        TIMER1_CFG = 0xc0000000 | (interval_in_ms*1000 - 1);
  193. +        /* unmask interrupt source */
  194. +        CPU_INT_EN = TIMER1_MASK;
  195. +    } else {
  196. +        COP_INT_EN = TIMER1_MASK;
  197. +    }
  198.  #else
  199.      /* We don't enable interrupts in the bootloader */
  200.      (void)interval_in_ms;
  201. @@ -508,6 +519,29 @@ void mutex_init(struct mutex *m)
  202.      m->thread = NULL;
  203.  }
  204.  
  205. +#ifdef CPU_PP
  206. +/* PortalPlayer chips have 2 cores, therefore need atomic mutexes */
  207. +
  208. +static inline bool test_and_set(bool *x, bool v)
  209. +{
  210. +    asm volatile (
  211. +        "swpb %0, %0, [%1]\n"
  212. +        : "+r"(v)
  213. +        : "r"(x)
  214. +    );
  215. +    return v;
  216. +}
  217. +
  218. +void mutex_lock(struct mutex *m)
  219. +{
  220. +    if (test_and_set(&m->locked,true))
  221. +    {
  222. +        /* Wait until the lock is open... */
  223. +        block_thread(&m->thread, 0);
  224. +    }
  225. +}
  226. +
  227. +#else
  228.  void mutex_lock(struct mutex *m)
  229.  {
  230.      if (m->locked)
  231. @@ -519,6 +553,7 @@ void mutex_lock(struct mutex *m)
  232.      /* ...and lock it */
  233.      m->locked = true;
  234.  }
  235. +#endif
  236.  
  237.  void mutex_unlock(struct mutex *m)
  238.  {
  239. diff --git a/firmware/system.c b/firmware/system.c
  240. index 6ba5dc6..0197a5e 100644
  241. --- a/firmware/system.c
  242. +++ b/firmware/system.c
  243. @@ -1223,34 +1223,62 @@ extern void ipod_mini_button_int(void);
  244.  
  245.  void irq(void)
  246.  {
  247. -    if (CPU_INT_STAT & TIMER1_MASK)
  248. -        TIMER1();
  249. -    else if (CPU_INT_STAT & TIMER2_MASK)
  250. -        TIMER2();
  251. -    else if (CPU_HI_INT_STAT & GPIO_MASK)
  252. -        ipod_mini_button_int();
  253. +    if(CURRENT_CORE == CPU)
  254. +    {
  255. +        if (CPU_INT_STAT & TIMER1_MASK)
  256. +            TIMER1();
  257. +        else if (CPU_INT_STAT & TIMER2_MASK)
  258. +            TIMER2();
  259. +        else if (CPU_HI_INT_STAT & GPIO_MASK)
  260. +            ipod_mini_button_int();
  261. +    } else {
  262. +        if (COP_INT_STAT & TIMER1_MASK)
  263. +            TIMER1();
  264. +        else if (COP_INT_STAT & TIMER2_MASK)
  265. +            TIMER2();
  266. +        else if (COP_HI_INT_STAT & GPIO_MASK)
  267. +            ipod_mini_button_int();
  268. +    }
  269.  }
  270.  #elif (defined IRIVER_H10) || (defined IRIVER_H10_5GB) || defined(ELIO_TPJ1022)
  271.  /* TODO: this should really be in the target tree, but moving it there caused
  272.     crt0.S not to find it while linking */
  273.  void irq(void)
  274.  {
  275. -    if (CPU_INT_STAT & TIMER1_MASK)
  276. -        TIMER1();
  277. -    else if (CPU_INT_STAT & TIMER2_MASK)
  278. -        TIMER2();
  279. +    if(CURRENT_CORE == CPU)
  280. +    {
  281. +        if (CPU_INT_STAT & TIMER1_MASK)
  282. +            TIMER1();
  283. +        else if (CPU_INT_STAT & TIMER2_MASK)
  284. +            TIMER2();
  285. +    } else {
  286. +        if (COP_INT_STAT & TIMER1_MASK)
  287. +            TIMER1();
  288. +        else if (COP_INT_STAT & TIMER2_MASK)
  289. +            TIMER2();
  290. +    }
  291.  }
  292.  #else
  293.  extern void ipod_4g_button_int(void);
  294.  
  295.  void irq(void)
  296.  {
  297. -    if (CPU_INT_STAT & TIMER1_MASK)
  298. -        TIMER1();
  299. -    else if (CPU_INT_STAT & TIMER2_MASK)
  300. -        TIMER2();
  301. -    else if (CPU_HI_INT_STAT & I2C_MASK)
  302. -        ipod_4g_button_int();
  303. +    if(CURRENT_CORE == CPU)
  304. +    {
  305. +        if (CPU_INT_STAT & TIMER1_MASK)
  306. +            TIMER1();
  307. +        else if (CPU_INT_STAT & TIMER2_MASK)
  308. +            TIMER2();
  309. +        else if (CPU_HI_INT_STAT & I2C_MASK)
  310. +            ipod_4g_button_int();
  311. +    } else {
  312. +        if (COP_INT_STAT & TIMER1_MASK)
  313. +            TIMER1();
  314. +        else if (COP_INT_STAT & TIMER2_MASK)
  315. +            TIMER2();
  316. +        else if (COP_HI_INT_STAT & I2C_MASK)
  317. +            ipod_4g_button_int();
  318. +    }
  319.  }
  320.  #endif
  321.  #endif /* BOOTLOADER */
  322. @@ -1303,43 +1331,47 @@ void set_cpu_frequency(long frequency)
  323.  {
  324.      unsigned long postmult;
  325.  
  326. -    if (frequency == CPUFREQ_NORMAL)
  327. -        postmult = CPUFREQ_NORMAL_MULT;
  328. -    else if (frequency == CPUFREQ_MAX)
  329. -        postmult = CPUFREQ_MAX_MULT;
  330. -    else
  331. -        postmult = CPUFREQ_DEFAULT_MULT;
  332. -    cpu_frequency = frequency;
  333. +    if (CURRENT_CORE == CPU)
  334. +    {
  335. +        if (frequency == CPUFREQ_NORMAL)
  336. +            postmult = CPUFREQ_NORMAL_MULT;
  337. +        else if (frequency == CPUFREQ_MAX)
  338. +            postmult = CPUFREQ_MAX_MULT;
  339. +        else
  340. +            postmult = CPUFREQ_DEFAULT_MULT;
  341. +        cpu_frequency = frequency;
  342.  
  343. -    /* Enable PLL? */
  344. -    outl(inl(0x70000020) | (1<<30), 0x70000020);
  345. +        /* Enable PLL? */
  346. +        outl(inl(0x70000020) | (1<<30), 0x70000020);
  347.  
  348. -    /* Select 24MHz crystal as clock source? */
  349. -    outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
  350. +        /* Select 24MHz crystal as clock source? */
  351. +        outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
  352.  
  353. -    /* Clock frequency = (24/8)*postmult */
  354. -    outl(0xaa020000 | 8 | (postmult << 8), 0x60006034);
  355. +        /* Clock frequency = (24/8)*postmult */
  356. +        outl(0xaa020000 | 8 | (postmult << 8), 0x60006034);
  357.  
  358. -    /* Wait for PLL relock? */
  359. -    udelay(2000);
  360. +        /* Wait for PLL relock? */
  361. +        udelay(2000);
  362.  
  363. -    /* Select PLL as clock source? */
  364. -    outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
  365. +        /* Select PLL as clock source? */
  366. +        outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
  367.  
  368.  #if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IRIVER_H10) || defined(IRIVER_H10_5GB)
  369. -    /* We don't know why the timer interrupt gets disabled on the PP5020
  370. -       based ipods, but without the following line, the 4Gs will freeze
  371. -       when CPU frequency changing is enabled.
  372. +        /* We don't know why the timer interrupt gets disabled on the PP5020
  373. +           based ipods, but without the following line, the 4Gs will freeze
  374. +           when CPU frequency changing is enabled.
  375.  
  376. -       Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used
  377. -       elsewhere to enable interrupts) doesn't work, we need "|=".
  378. +           Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used
  379. +           elsewhere to enable interrupts) doesn't work, we need "|=".
  380.  
  381. -       It's not needed on the PP5021 and PP5022 ipods.
  382. -    */
  383. +           It's not needed on the PP5021 and PP5022 ipods.
  384. +        */
  385.  
  386. -    /* unmask interrupt source */
  387. -    CPU_INT_EN |= TIMER1_MASK;
  388. +        /* unmask interrupt source */
  389. +        CPU_INT_EN |= TIMER1_MASK;
  390. +        COP_INT_EN |= TIMER1_MASK;
  391.  #endif
  392. +    }
  393.  }
  394.  #elif !defined(BOOTLOADER)
  395.  void ipod_set_cpu_frequency(void)
  396. @@ -1363,21 +1395,24 @@ #endif
  397.  void system_init(void)
  398.  {
  399.  #ifndef BOOTLOADER
  400. -    /* The hw revision is written to the last 4 bytes of SDRAM by the
  401. -       bootloader - we save it before Rockbox overwrites it. */
  402. -    ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
  403. -
  404. -    /* disable all irqs */
  405. -    outl(-1, 0x60001138);
  406. -    outl(-1, 0x60001128);
  407. -    outl(-1, 0x6000111c);
  408. -
  409. -    outl(-1, 0x60001038);
  410. -    outl(-1, 0x60001028);
  411. -    outl(-1, 0x6000101c);
  412. +    if (CURRENT_CORE == CPU)
  413. +    {
  414. +        /* The hw revision is written to the last 4 bytes of SDRAM by the
  415. +           bootloader - we save it before Rockbox overwrites it. */
  416. +        ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
  417. +
  418. +        /* disable all irqs */
  419. +        outl(-1, 0x60001138);
  420. +        outl(-1, 0x60001128);
  421. +        outl(-1, 0x6000111c);
  422. +
  423. +        outl(-1, 0x60001038);
  424. +        outl(-1, 0x60001028);
  425. +        outl(-1, 0x6000101c);
  426.  #ifndef HAVE_ADJUSTABLE_CPU_FREQ
  427. -    ipod_set_cpu_frequency();
  428. +        ipod_set_cpu_frequency();
  429.  #endif
  430. +    }
  431.      ipod_init_cache();
  432.  #endif
  433.  }
  434. @@ -1401,10 +1436,18 @@ extern void TIMER2(void);
  435.  
  436.  void irq(void)
  437.  {
  438. -    if (CPU_INT_STAT & TIMER1_MASK)
  439. -        TIMER1();
  440. -    else if (CPU_INT_STAT & TIMER2_MASK)
  441. -        TIMER2();
  442. +    if(CURRENT_CORE == CPU)
  443. +    {
  444. +        if (CPU_INT_STAT & TIMER1_MASK)
  445. +            TIMER1();
  446. +        else if (CPU_INT_STAT & TIMER2_MASK)
  447. +            TIMER2();
  448. +    } else {
  449. +        if (COP_INT_STAT & TIMER1_MASK)
  450. +            TIMER1();
  451. +        else if (COP_INT_STAT & TIMER2_MASK)
  452. +            TIMER2();
  453. +    }
  454.  }
  455.  
  456.  #endif
  457. @@ -1453,29 +1496,32 @@ void set_cpu_frequency(long frequency)
  458.  {
  459.      unsigned long postmult;
  460.  
  461. -    if (frequency == CPUFREQ_NORMAL)
  462. -        postmult = CPUFREQ_NORMAL_MULT;
  463. -    else if (frequency == CPUFREQ_MAX)
  464. -        postmult = CPUFREQ_MAX_MULT;
  465. -    else
  466. -        postmult = CPUFREQ_DEFAULT_MULT;
  467. -    cpu_frequency = frequency;
  468. +    if (CURRENT_CORE == CPU)
  469. +    {
  470. +        if (frequency == CPUFREQ_NORMAL)
  471. +            postmult = CPUFREQ_NORMAL_MULT;
  472. +        else if (frequency == CPUFREQ_MAX)
  473. +            postmult = CPUFREQ_MAX_MULT;
  474. +        else
  475. +            postmult = CPUFREQ_DEFAULT_MULT;
  476. +        cpu_frequency = frequency;
  477.  
  478. -    outl(0x02, 0xcf005008);
  479. -    outl(0x55, 0xcf00500c);
  480. -    outl(0x6000, 0xcf005010);
  481. +        outl(0x02, 0xcf005008);
  482. +        outl(0x55, 0xcf00500c);
  483. +        outl(0x6000, 0xcf005010);
  484.  
  485. -    /* Clock frequency = (24/8)*postmult */
  486. -    outl(8, 0xcf005018);
  487. -    outl(postmult, 0xcf00501c);
  488. +        /* Clock frequency = (24/8)*postmult */
  489. +        outl(8, 0xcf005018);
  490. +        outl(postmult, 0xcf00501c);
  491.  
  492. -    outl(0xe000, 0xcf005010);
  493. +        outl(0xe000, 0xcf005010);
  494.  
  495. -    /* Wait for PLL relock? */
  496. -    udelay(2000);
  497. +        /* Wait for PLL relock? */
  498. +        udelay(2000);
  499.  
  500. -    /* Select PLL as clock source? */
  501. -    outl(0xa8, 0xcf00500c);
  502. +        /* Select PLL as clock source? */
  503. +        outl(0xa8, 0xcf00500c);
  504. +    }
  505.  }
  506.  #elif !defined(BOOTLOADER)
  507.  static void ipod_set_cpu_speed(void)
  508. @@ -1506,13 +1552,16 @@ #endif
  509.  void system_init(void)
  510.  {
  511.  #ifndef BOOTLOADER
  512. -    ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
  513. -    outl(-1, 0xcf00101c);
  514. -    outl(-1, 0xcf001028);
  515. -    outl(-1, 0xcf001038);
  516. +    if (CURRENT_CORE == CPU)
  517. +    {
  518. +        ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
  519. +        outl(-1, 0xcf00101c);
  520. +        outl(-1, 0xcf001028);
  521. +        outl(-1, 0xcf001038);
  522.  #ifndef HAVE_ADJUSTABLE_CPU_FREQ
  523. -    ipod_set_cpu_speed();
  524. +        ipod_set_cpu_speed();
  525.  #endif
  526. +    }
  527.      ipod_init_cache();
  528.  #endif
  529.  }
  530. diff --git a/firmware/target/arm/crt0-pp.S b/firmware/target/arm/crt0-pp.S
  531. index 3bf2805..7badc69 100644
  532. --- a/firmware/target/arm/crt0-pp.S
  533. +++ b/firmware/target/arm/crt0-pp.S
  534. @@ -285,6 +285,19 @@ cop_init:
  535.      strhi  r4, [r2], #4
  536.      bhi    2b
  537.  
  538. +    /* Set up stack for IRQ mode */
  539. +    msr    cpsr_c, #0xd2
  540. +    ldr    sp, =cop_irq_stack
  541. +    /* Set up stack for FIQ mode */
  542. +    msr    cpsr_c, #0xd1
  543. +    ldr    sp, =fiq_stack
  544. +
  545. +    /* Let abort and undefined modes use IRQ stack */
  546. +    msr    cpsr_c, #0xd7
  547. +    ldr    sp, =cop_irq_stack
  548. +    msr    cpsr_c, #0xdb
  549. +    ldr    sp, =cop_irq_stack
  550. +
  551.      ldr    sp, =cop_stackend
  552.      bl     cop_main
  553.      
  554. @@ -368,6 +381,10 @@ #endif
  555.      .space 256*4
  556.  irq_stack:
  557.  
  558. +/* 256 words of COP IRQ stack */
  559. +    .space 256*4
  560. +cop_irq_stack:
  561. +
  562.  /* 256 words of FIQ stack */
  563.      .space 256*4
  564.  fiq_stack:
  565. diff --git a/firmware/thread.c b/firmware/thread.c
  566. index 1662740..4eada84 100644
  567. --- a/firmware/thread.c
  568. +++ b/firmware/thread.c
  569. @@ -338,10 +338,13 @@ #ifdef CPU_COLDFIRE
  570.  #elif CONFIG_CPU == SH7034
  571.          and_b(0x7F, &SBYCR);
  572.          asm volatile ("sleep");
  573. -#elif CONFIG_CPU == PP5020
  574. +#elif defined (CPU_PP)
  575.          /* This should sleep the CPU. It appears to wake by itself on
  576.             interrupts */
  577. -        CPU_CTL = 0x80000000;
  578. +        if (CURRENT_CORE == CPU)
  579. +            CPU_CTL = PROC_SLEEP;
  580. +        else
  581. +            COP_CTL = PROC_SLEEP;
  582.  #elif CONFIG_CPU == TCC730
  583.             /* Sleep mode is triggered by the SYS instr on CalmRisc16.
  584.           * Unfortunately, the manual doesn't specify which arg to use.
  585. @@ -690,7 +693,8 @@ void init_threads(void)
  586.  {
  587.      unsigned int core = CURRENT_CORE;
  588.  
  589. -    memset(cores, 0, sizeof cores);
  590. +    if (core == CPU)
  591. +        memset(cores, 0, sizeof cores);
  592.      cores[core].sleeping = NULL;
  593.      cores[core].running = NULL;
  594.      cores[core].threads[0].name = main_thread_name;

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