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Monday, April 23rd, 2012 at 10:41:49pm UTC 

  1. --- a/r4/FPGA.sch
  2. +++ b/r4/FPGA.sch
  3. -EESchema Schematic File Version 2  date Mon 23 Apr 2012 15:23:10 CST
  4. +EESchema Schematic File Version 2  date Mon Apr 23 12:41:34 2012
  5. -LIBS:m1-cache
  6. -EELAYER 24  0
  7. +LIBS:powered
  8. +EELAYER 25  0
  9. -$Descr A2 23400 16535
  10. +$Descr A2 23386 16535
  11. +encoding utf-8
  12. -       15800 7300 14650 7300
  13. -       15800 7200 14650 7200
  14. -       15800 7000 14650 7000
  15. -       15800 7100 14650 7100
  16. +       14650 7000 15800 7000
  17. +       14650 7100 15800 7100
  18. +       14650 7200 15800 7200
  19. +       14650 7300 15800 7300

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