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Monday, June 14th, 2010 at 6:27:56pm UTC 

  1. Index: apps/debug_menu.c
  2. ===================================================================
  3. --- apps/debug_menu.c   (revision 26846)
  4. +++ apps/debug_menu.c   (working copy)
  5. @@ -2369,25 +2369,16 @@
  6.  #endif /* TEA5767 */
  7.  #if (CONFIG_TUNER & SI4700)
  8.      struct si4700_dbg_info nfo;
  9. +    int i;
  10.      si4700_dbg_info(&nfo);
  11.      simplelist_addline(SIMPLELIST_ADD_LINE, "SI4700 regs:");
  12.      /* Registers */
  13. -    simplelist_addline(SIMPLELIST_ADD_LINE,
  14. -             "%04X %04X %04X %04X",
  15. -             (unsigned)nfo.regs[0], (unsigned)nfo.regs[1],
  16. -             (unsigned)nfo.regs[2], (unsigned)nfo.regs[3]);
  17. -    simplelist_addline(SIMPLELIST_ADD_LINE,
  18. -             "%04X %04X %04X %04X",
  19. -             (unsigned)nfo.regs[4], (unsigned)nfo.regs[5],
  20. -             (unsigned)nfo.regs[6], (unsigned)nfo.regs[7]);
  21. -    simplelist_addline(SIMPLELIST_ADD_LINE,
  22. -             "%04X %04X %04X %04X",
  23. -             (unsigned)nfo.regs[8], (unsigned)nfo.regs[9],
  24. -             (unsigned)nfo.regs[10], (unsigned)nfo.regs[11]);
  25. -    simplelist_addline(SIMPLELIST_ADD_LINE,
  26. -             "%04X %04X %04X %04X",
  27. -             (unsigned)nfo.regs[12], (unsigned)nfo.regs[13],
  28. -             (unsigned)nfo.regs[14], (unsigned)nfo.regs[15]);
  29. +    for (i = 0; i < 8; i++) {
  30. +        simplelist_addline(SIMPLELIST_ADD_LINE,
  31. +                 "%04X %04X %04X %04X",
  32. +                 (unsigned)nfo.regs[4*i], (unsigned)nfo.regs[4*i+1],
  33. +                 (unsigned)nfo.regs[4*i+2], (unsigned)nfo.regs[4*i+3]);
  34. +    }
  35.  #endif /* SI4700 */
  36.      return ACTION_REDRAW;
  37.  }
  38. @@ -2400,7 +2391,8 @@
  39.      simplelist_addline(SIMPLELIST_ADD_LINE, "HW detected: %s",
  40.                         radio_hardware_present() ? "yes" : "no");
  41.  
  42. -    info.action_callback = radio_hardware_present()?radio_callback : NULL;
  43. +//    info.action_callback = radio_hardware_present()?radio_callback : NULL;
  44. +    info.action_callback = radio_callback;
  45.      info.hide_selection = true;
  46.      return simplelist_show_list(&info);
  47.  }
  48. Index: firmware/export/si4700.h
  49. ===================================================================
  50. --- firmware/export/si4700.h    (revision 26846)
  51. +++ firmware/export/si4700.h    (working copy)
  52. @@ -38,7 +38,7 @@
  53.  
  54.  struct si4700_dbg_info
  55.  {
  56. -    uint16_t regs[16];  /* Read registers */
  57. +    uint16_t regs[32];  /* Read registers */
  58.  };
  59.  
  60.  void si4700_init(void);
  61. Index: firmware/drivers/tuner/si4700.c
  62. ===================================================================
  63. --- firmware/drivers/tuner/si4700.c     (revision 26846)
  64. +++ firmware/drivers/tuner/si4700.c     (working copy)
  65. @@ -7,9 +7,10 @@
  66.   *                     \/            \/     \/    \/            \/
  67.   * $Id$
  68.   *
  69. - * Tuner "middleware" for Silicon Labs SI4700 chip
  70. + * Tuner "middleware" for Unidentified Silicon Labs chip present in some
  71. + * Sansa Clip+ players
  72.   *
  73. - * Copyright (C) 2008 Nils Wallmnius
  74. + * Copyright (C) 2010 Bertrik Sikken
  75.   *
  76.   * This program is free software; you can redistribute it and/or
  77.   * modify it under the terms of the GNU General Public License
  78. @@ -30,200 +31,73 @@
  79.  #include "fmradio.h"
  80.  #include "fmradio_i2c.h" /* physical interface driver */
  81.  
  82. -/* some models use the internal 32 kHz oscillator which needs special attention
  83. -   during initialisation, power-up and power-down.
  84. -*/
  85. -#if defined(SANSA_CLIP) || defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2)
  86. -#define USE_INTERNAL_OSCILLATOR
  87. -#elif defined(TOSHIBA_GIGABEAT_S)
  88. -#define SI4700_GPIO_SETUP (SYSCONFIG1_GPIO1_HI_Z | \
  89. -                           SYSCONFIG1_GPIO2_HI_Z | \
  90. -                           SYSCONFIG1_GPIO3_MO_ST_I)
  91. -extern int si4700_st(void);
  92. -#endif
  93. +#define SEEK_THRESHOLD 0x10
  94.  
  95. -#ifndef SI4700_GPIO_SETUP
  96. -#define SI4700_GPIO_SETUP 0
  97. -#endif
  98. -
  99. -#define SEEK_THRESHOLD 0x16
  100. -
  101.  #define I2C_ADR 0x20
  102.  
  103.  /** Registers and bits - "x" denotes Si4702/03 only (so they say) **/
  104. -#define DEVICEID    0x0
  105. -#define CHIPID      0x1
  106.  #define POWERCFG    0x2
  107.  #define CHANNEL     0x3
  108.  #define SYSCONFIG1  0x4
  109.  #define SYSCONFIG2  0x5
  110.  #define SYSCONFIG3  0x6
  111. -#define TEST1       0x7
  112. -#define TEST2       0x8
  113. -#define BOOTCONFIG  0x9
  114. -#define STATUSRSSI  0xA
  115. -#define READCHAN    0xB
  116. -#define RDSA        0xC /* x */
  117. -#define RDSB        0xD /* x */
  118. -#define RDSC        0xE /* x */
  119. -#define RDSD        0xF /* x */
  120.  
  121. -/* DEVICEID (0x0) */
  122. -#define DEVICEID_PN         (0xf << 12)
  123. -    /* 0x01 = Si4700/01 */
  124. -    /* 0x01 = Si4702/03 */
  125. -#define DEVICEID_MFGID      (0xfff << 0)
  126. -    /* always 0x242 */
  127. +#define READCHAN    0xA
  128. +#define STATUSRSSI  0xB
  129. +#define IDENT       0xC
  130.  
  131. -/* CHIPID (0x1) */
  132.  
  133. -#if 0 /* Informational */
  134. -/* Si4700/01 */
  135. -#define CHIPID_REV          (0x3f << 10)
  136. -#define CHIPID_DEV          (0x1 << 9)
  137. -    /* 0 before powerup */
  138. -    /* 0 after powerup = Si4700 */
  139. -    /* 1 after powerup = Si4701 */
  140. -#define CHIPID_FIRMWARE     (0xff << 0)
  141. -
  142. -/* Si4702/03 */
  143. -#define CHIPID_REV          (0x3f << 10)
  144. -#define CHIPID_DEV          (0xf << 6)
  145. -    /* 0000 before PU = Si4702 */
  146. -    /* 0001 after PU = Si4702 */
  147. -    /* 1000 before PU = Si4703 */
  148. -    /* 1001 after PU = Si4703 */
  149. -#define CHIPID_FIRMWARE     (0x3f << 0)
  150. -#endif /* 0 */
  151. -
  152.  /* POWERCFG (0x2) */
  153. -#define POWERCFG_DSMUTE     (0x1 << 15)
  154.  #define POWERCFG_DMUTE      (0x1 << 14)
  155.  #define POWERCFG_MONO       (0x1 << 13)
  156. -#define POWERCFG_RDSM       (0x1 << 11) /* x */
  157. -#define POWERCFG_SKMODE     (0x1 << 10)
  158. -#define POWERCFG_SEEKUP     (0x1 <<  9)
  159. -#define POWERCFG_SEEK       (0x1 <<  8)
  160. -#define POWERCFG_DISABLE    (0x1 <<  6)
  161.  #define POWERCFG_ENABLE     (0x1 <<  0)
  162.  
  163.  /* CHANNEL (0x3) */
  164. -#define CHANNEL_TUNE        (0x1 << 15)
  165. -#define CHANNEL_CHAN        (0x3ff << 0)
  166. -    #define CHANNEL_CHANw(x) ((x) & CHANNEL_CHAN)
  167. +#define CHANNEL_CHAN        (0x3ff << 6)
  168. +    #define CHANNEL_CHANw(x) (((x) << 6) & CHANNEL_CHAN)
  169. +#define CHANNEL_TUNE        (0x1 << 4)
  170. +#define CHANNEL_BAND        (0x3 << 2)
  171. +    #define CHANNEL_BANDw(x)        (((x) << 2) & CHANNEL_BAND)
  172. +    #define CHANNEL_BANDr(x)        (((x) & CHANNEL_BAND) >> 2)
  173. +    #define CHANNEL_BAND_875_1080   (0x0 << 2) /* tenth-megahertz */
  174. +    #define CHANNEL_BAND_760_1080   (0x1 << 2)
  175. +    #define CHANNEL_BAND_760_900    (0x2 << 2)
  176. +#define CHANNEL_SPACE       (0x3 << 0)
  177. +    #define CHANNEL_SPACEw(x)  (((x) << 0) & CHANNEL_SPACE)
  178. +    #define CHANNEL_SPACEr(x)  (((x) & CHANNEL_SPACE) >> 0)
  179. +    #define CHANNEL_SPACE_200KHZ    (0x0 << 0)
  180. +    #define CHANNEL_SPACE_100KHZ    (0x1 << 0)
  181. +    #define CHANNEL_SPACE_50KHZ     (0x2 << 0)
  182.  
  183.  /* SYSCONFIG1 (0x4) */
  184. -#define SYSCONFIG1_RDSIEN   (0x1 << 15) /* x */
  185. -#define SYSCONFIG1_STCIEN   (0x1 << 14)
  186. -#define SYSCONFIG1_RDS      (0x1 << 12) /* x */
  187.  #define SYSCONFIG1_DE       (0x1 << 11)
  188. -#define SYSCONFIG1_AGCD     (0x1 << 10)
  189. -#define SYSCONFIG1_BLNDADJ  (0x3 <<  6)
  190. -    #define SYSCONFIG1_BLNDADJ_31_39_RSSI (0x0 << 6)
  191. -    #define SYSCONFIG1_BLNDADJ_37_55_RSSI (0x1 << 6)
  192. -    #define SYSCONFIG1_BLNDADJ_19_37_RSSI (0x2 << 6)
  193. -    #define SYSCONFIG1_BLNDADJ_25_43_RSSI (0x3 << 6)
  194. -#define SYSCONFIG1_GPIO3    (0x3 <<  4)
  195. -    #define SYSCONFIG1_GPIO3_HI_Z       (0x0 << 4)
  196. -    #define SYSCONFIG1_GPIO3_MO_ST_I    (0x1 << 4)
  197. -    #define SYSCONFIG1_GPIO3_LOW        (0x2 << 4)
  198. -    #define SYSCONFIG1_GPIO3_HI         (0x3 << 4)
  199. -#define SYSCONFIG1_GPIO2    (0x3 <<  2)
  200. -    #define SYSCONFIG1_GPIO2_HI_Z       (0x0 << 2)
  201. -    #define SYSCONFIG1_GPIO2_STC_RDS_I  (0x1 << 2)
  202. -    #define SYSCONFIG1_GPIO2_LOW        (0x2 << 2)
  203. -    #define SYSCONFIG1_GPIO2_HI         (0x3 << 2)
  204. -#define SYSCONFIG1_GPIO1    (0x3 <<  0)
  205. -    #define SYSCONFIG1_GPIO1_HI_Z       (0x0 << 0)
  206. -    #define SYSCONFIG1_GPIO1_LOW        (0x2 << 0)
  207. -    #define SYSCONFIG1_GPIO1_HI         (0x3 << 0)
  208.  
  209. -/* SYSCONFIG2 (0x5) */
  210. -#define SYSCONFIG2_SEEKTH   (0xff << 8)
  211. -    #define SYSCONFIG2_SKEETHw(x) (((x) << 8) & SYSCONFIG2_SEEKTH)
  212. -#define SYSCONFIG2_BAND     (0x3 << 6)
  213. -    #define SYSCONFIG2_BANDw(x)   (((x) << 6) & SYSCONFIG2_BAND)
  214. -    #define SYSCONFIG2_BANDr(x)   (((x) & SYSCONFIG2_BAND) >> 6)
  215. -    #define SYSCONFIG2_BAND_875_1080    (0x0 << 6) /* tenth-megahertz */
  216. -    #define SYSCONFIG2_BAND_760_1080    (0x1 << 6)
  217. -    #define SYSCONFIG2_BAND_760_900     (0x2 << 6)
  218. -#define SYSCONFIG2_SPACE    (0x3 << 4)
  219. -    #define SYSCONFIG2_SPACEw(x)  (((x) << 4) & SYSCONFIG2_SPACE)
  220. -    #define SYSCONFIG2_SPACEr(x)  (((x) & SYSCONFIG2_SPACE) >> 4)
  221. -    #define SYSCONFIG2_SPACE_200KHZ     (0x0 << 4)
  222. -    #define SYSCONFIG2_SPACE_100KHZ     (0x1 << 4)
  223. -    #define SYSCONFIG2_SPACE_50KHZ      (0x2 << 4)
  224. -/* 4700/01            0000=mute,0001=-28dBFS..2dB steps..1111= +0dBFS */
  225. -/* 4702/03: VOLEXT=0: 0000=mute,0001=-28dBFS..2dB steps..1111= +0dBFS */
  226. -/*          VOLEXT=1: 0000=mute,0001=-58dBFS..2dB steps..1111=-30dBFS */
  227. -#define SYSCONFIG2_VOLUME   (0xf << 0)
  228. -    #define SYSCONFIG2_VOLUMEw(x) ((x) & SYSCONFIG2_VOLUME)
  229. -
  230. -/* SYSCONFIG3 (0x6) */
  231. -#define SYSCONFIG3_SMUTER   (0x3 << 14)
  232. -    #define SYSCONFIG3_SMUTER_FASTEST   (0x0 << 14)
  233. -    #define SYSCONFIG3_SMUTER_FAST      (0x1 << 14)
  234. -    #define SYSCONFIG3_SMUTER_SLOW      (0x2 << 14)
  235. -    #define SYSCONFIG3_SMUTER_SLOWEST   (0x3 << 14)
  236. -#define SYSCONFIG3_SMUTEA   (0x3 << 12)
  237. -    #define SYSCONFIG3_SMUTEA_16DB      (0x0 << 12)
  238. -    #define SYSCONFIG3_SMUTEA_14DB      (0x1 << 12)
  239. -    #define SYSCONFIG3_SMUTEA_12DB      (0x2 << 12)
  240. -    #define SYSCONFIG3_SMUTEA_10DB      (0x3 << 12)
  241. -#define SYSCONFIG3_VOLEXT   (0x1 << 8) /* x */
  242. -#define SYSCONFIG3_SKSNR    (0xf << 4)
  243. -    #define SYSCONFIG3_SKSNRw(x) (((x) << 4) & SYSCONFIG3_SKSNR)
  244. -#define SYSCONFIG3_SKCNT    (0xf << 0)
  245. -    #define SYSCONFIG3_SKCNTw(x) (((x) << 0) & SYSCONFIG3_SKCNT)
  246. -
  247. -/* TEST1 (0x7) */
  248. -/* 4700/01: 15=always 0, 13:0 = write with preexisting values! */
  249. -/* 4702/03:              13:0 = write with preexisting values! */
  250. -#define TEST1_XOSCEN        (0x1 << 15) /* x */
  251. -#define TEST1_AHIZEN        (0x1 << 14)
  252. -
  253. -/* TEST2 (0x8) */
  254. -/* 15:0 = write with preexisting values! */
  255. -
  256. -/* BOOTCONFIG (0x9) */
  257. -/* 15:0 = write with preexisting values! */
  258. -
  259. -/* STATUSRSSI (0xA) */
  260. -#define STATUSRSSI_RDSR     (0x1 << 15) /* x */
  261. -#define STATUSRSSI_STC      (0x1 << 14)
  262. -#define STATUSRSSI_SFBL     (0x1 << 13)
  263. -#define STATUSRSSI_AFCRL    (0x1 << 12)
  264. -#define STATUSRSSI_RDSS     (0x1 << 11) /* x */
  265. -#define STATUSRSSI_BLERA    (0x3 <<  9) /* x */
  266. -#define STATUSRSSI_ST       (0x1 <<  8)
  267. -#define STATUSRSSI_RSSI     (0xff << 0)
  268. -    #define STATUSRSSI_RSSIr(x) ((x) & 0xff)
  269. -
  270. -/* READCHAN (0xB) */
  271. -#define READCHAN_BLERB      (0x3 << 14) /* x */
  272. -#define READCHAN_BLERC      (0x3 << 12) /* x */
  273. -#define READCHAN_BLERD      (0x3 << 10) /* x */
  274. +/* READCHAN (0xA) */
  275.  #define READCHAN_READCHAN   (0x3ff << 0)
  276. +    #define READCHAN_READCHANr(x) (((x) & READCHAN_READCHAN) >> 0)
  277. +#define READCHAN_STC        (0x1 << 14)
  278.  
  279. -/* RDSA-D (0xC-0xF) */
  280. -/* 4702/03: RDS Block A-D data */
  281. +/* STATUSRSSI (0xB) */
  282. +#define STATUSRSSI_RSSI     (0x3F << 10)
  283. +    #define STATUSRSSI_RSSIr(x) (((x) & STATUSRSSI_RSSI) >> 10)
  284. +#define STATUSRSSI_AFCRL    (0x1 << 8)
  285.  
  286.  static bool tuner_present = false;
  287.  static int curr_frequency = 87500000; /* Current station frequency (HZ) */
  288. -static uint16_t cache[16];
  289. +static uint16_t cache[32];
  290.  
  291.  /* reads <len> registers from radio at offset 0x0A into cache */
  292.  static void si4700_read(int len)
  293.  {
  294.      int i;
  295. -    unsigned char buf[32];
  296. +    unsigned char buf[64];
  297.      unsigned char *ptr = buf;
  298.      uint16_t data;
  299.      
  300.      fmradio_i2c_read(I2C_ADR, buf, len * 2);
  301.      for (i = 0; i < len; i++) {
  302.          data = ptr[0] << 8 | ptr[1];
  303. -        cache[(i + STATUSRSSI) & 0xF] = data;
  304. +        cache[(i + READCHAN) & 0x1F] = data;
  305.          ptr += 2;
  306.      }
  307.  }
  308. @@ -232,12 +106,12 @@
  309.  static void si4700_write(int len)
  310.  {
  311.      int i;
  312. -    unsigned char buf[32];
  313. +    unsigned char buf[64];
  314.      unsigned char *ptr = buf;
  315.      uint16_t data;
  316.  
  317.      for (i = 0; i < len; i++) {
  318. -        data = cache[(i + POWERCFG) & 0xF];
  319. +        data = cache[(i + POWERCFG) & 0x1F];
  320.          *ptr++ = (data >> 8) & 0xFF;
  321.          *ptr++ = data & 0xFF;
  322.      }
  323. @@ -249,16 +123,21 @@
  324.   * using the 3-wire interface. */
  325.  static uint16_t si4700_read_reg(int reg)
  326.  {
  327. -    si4700_read(((reg - STATUSRSSI) & 0xF) + 1);
  328. +    si4700_read(((reg - READCHAN) & 0x1F) + 1);
  329.      return cache[reg];
  330.  }
  331.  
  332.  static void si4700_write_reg(int reg, uint16_t value)
  333.  {
  334.      cache[reg] = value;
  335. -    si4700_write(((reg - POWERCFG) & 0xF) + 1);
  336. +//    si4700_write(((reg - POWERCFG) & 0xF) + 1);
  337.  }
  338.  
  339. +static void si4700_write_cache(void)
  340. +{
  341. +    si4700_write(5);
  342. +}
  343. +
  344.  static void si4700_write_masked(int reg, uint16_t bits, uint16_t mask)
  345.  {
  346.      si4700_write_reg(reg, (cache[reg] & ~mask) | (bits & mask));
  347. @@ -274,106 +153,89 @@
  348.      si4700_write_reg(reg, cache[reg] & ~mask);
  349.  }
  350.  
  351. -#if (SI4700_GPIO_SETUP & SYSCONFIG1_GPIO3) != SYSCONFIG1_GPIO3_MO_ST_I
  352. -/* Poll i2c for the stereo status */
  353. -static inline int si4700_st(void)
  354. -{
  355. -    return (si4700_read_reg(STATUSRSSI) & STATUSRSSI_ST) >> 8;
  356. -}
  357. -#endif
  358. -
  359.  static void si4700_sleep(int snooze)
  360.  {
  361.      if (snooze)
  362.      {
  363.          /** power down **/
  364. -        /* ENABLE high, DISABLE high */
  365. -        si4700_write_set(POWERCFG,
  366. -                         POWERCFG_DISABLE | POWERCFG_ENABLE);
  367. -        /* Bits self-clear once placed in powerdown. */
  368. -        cache[POWERCFG] &= ~(POWERCFG_DISABLE | POWERCFG_ENABLE);
  369. +        si4700_write_masked(POWERCFG, 0, 0xFF);
  370.      }
  371.      else
  372.      {
  373. -        /** power up **/
  374. -        /* ENABLE high, DISABLE low */
  375. -        si4700_write_masked(POWERCFG, POWERCFG_ENABLE,
  376. -                            POWERCFG_DISABLE | POWERCFG_ENABLE);
  377. -        sleep(110 * HZ / 1000);
  378. -
  379. -        /* init register cache */
  380. -        si4700_read(16);
  381. -
  382. -#if SI4700_GPIO_SETUP != 0
  383. -        si4700_write_masked(SYSCONFIG1, SI4700_GPIO_SETUP,
  384. -                            SYSCONFIG1_GPIO1 | SYSCONFIG1_GPIO2 |
  385. -                            SYSCONFIG1_GPIO3);
  386. -#endif
  387. -        si4700_write_masked(SYSCONFIG2,
  388. -                            SYSCONFIG2_SKEETHw(SEEK_THRESHOLD) |
  389. -                            SYSCONFIG2_VOLUMEw(0xF),
  390. -                            SYSCONFIG2_VOLUME | SYSCONFIG2_SEEKTH);
  391. +        si4700_write_masked(POWERCFG, 1, 0xFF);
  392.      }
  393. +    si4700_write_cache();
  394.  }
  395.  
  396. -void si4700_init(void)
  397. +static const uint16_t initvals[32] = {
  398. +    0x8110, 0x4580, 0xC401, 0x1B90,
  399. +    0x0400, 0x866F, 0x8000, 0x4712,
  400. +    0x5EC6, 0x0000, 0x406E, 0x2D80,
  401. +    0x5803, 0x5804, 0x5804, 0x5804,
  402. +   
  403. +    0x0047, 0x9000, 0xF587, 0x0009,
  404. +    0x00F1, 0x41C0, 0x41E0, 0x506F,
  405. +    0x5592, 0x007D, 0x10A0, 0x0780,
  406. +    0x311D, 0x4006, 0x1F9B, 0x4C2B,
  407. +#if 0   /* there only seem to be 32 registers ... */
  408. +    0x153F, 0xAF40, 0x0481, 0x1B2A,
  409. +    0x2D04, 0x802F, 0x178A, 0xD349,
  410. +    0x1142
  411. +#endif
  412. +};
  413. +
  414. +bool fmclipplus_detect(void)
  415.  {
  416. -    tuner_power(true);
  417. +    return ((si4700_read_reg(IDENT) & 0xFF00) == 0x5800);
  418. + }
  419.  
  420. -    /* read all registers */
  421. -    si4700_read(16);
  422. -    si4700_sleep(0);
  423. -
  424. -    /* check device id */
  425. -    if (cache[DEVICEID] == 0x1242)
  426. -    {
  427. +void si4700_init(void)
  428. +{
  429. +    if (fmclipplus_detect()) {
  430.          tuner_present = true;
  431.  
  432. -#ifdef USE_INTERNAL_OSCILLATOR
  433. -        /* Enable the internal oscillator
  434. -          (Si4702-16 needs this register to be initialised to 0x100) */
  435. -        si4700_write_set(TEST1, TEST1_XOSCEN | 0x100);
  436. -        sleep(HZ/2);
  437. -#endif
  438. -    }
  439. +        // send pre-initialisation value
  440. +        si4700_write_reg(POWERCFG, 0x200);
  441. +        si4700_write(2);
  442. +        sleep(HZ * 10 / 100);
  443.  
  444. -    si4700_sleep(1);
  445. -
  446. -    tuner_power(false);
  447. +        // write initialisation values
  448. +        memcpy(cache, initvals, sizeof(cache));
  449. +        si4700_write(32);
  450. +        sleep(HZ * 70 / 1000);
  451. +    }
  452.  }
  453.  
  454.  static void si4700_set_frequency(int freq)
  455.  {
  456. -    static const unsigned int spacings[3] =
  457. -    {
  458. -          200000, /* SYSCONFIG2_SPACE_200KHZ */
  459. -          100000, /* SYSCONFIG2_SPACE_100KHZ */
  460. -           50000, /* SYSCONFIG2_SPACE_50KHZ  */
  461. -    };
  462. -    static const unsigned int bands[3] =
  463. -    {
  464. -        87500000, /* SYSCONFIG2_BAND_875_1080 */
  465. -        76000000, /* SYSCONFIG2_BAND_760_1080 */
  466. -        76000000, /* SYSCONFIG2_BAND_760_900  */
  467. -    };
  468. +    int i;
  469.  
  470.      /* check BAND and spacings */
  471. -    int space = SYSCONFIG2_SPACEr(cache[SYSCONFIG2]);
  472. -    int band = SYSCONFIG2_BANDr(cache[SYSCONFIG2]);
  473. -    int chan = (freq - bands[band]) / spacings[space];
  474. +    si4700_read_reg(STATUSRSSI);
  475. +    int start = CHANNEL_BANDr(cache[CHANNEL]) & 1 ? 76000000 : 87000000;
  476. +    int chan = (freq - start) / 50000;
  477.  
  478.      curr_frequency = freq;
  479.  
  480. -    si4700_write_reg(CHANNEL, CHANNEL_CHANw(chan) | CHANNEL_TUNE);
  481. -
  482. -    do
  483. -    {
  484. -        /* tuning should be done within 60 ms according to the datasheet */
  485. -        sleep(HZ * 60 / 1000);
  486. +    for (i = 0; i < 5; i++) {
  487. +        /* start tune */
  488. +        si4700_write_masked(CHANNEL, CHANNEL_CHANw(chan) | CHANNEL_TUNE, CHANNEL_CHAN | CHANNEL_TUNE);
  489. +        si4700_write_cache();
  490. +       
  491. +        /* wait a bit while tuning */
  492. +        sleep(HZ * 70 / 1000);
  493. +        si4700_write_clear(CHANNEL, CHANNEL_TUNE); /* Set TUNE low */
  494. +        si4700_write_cache();
  495. +       
  496. +        /* are we tuned yet? */
  497. +        si4700_read_reg(STATUSRSSI);
  498. +        if (cache[READCHAN] & READCHAN_STC) {
  499. +            if (READCHAN_READCHANr(cache[READCHAN]) == chan) {
  500. +                // yay tuned
  501. +                break;
  502. +            }
  503. +        }
  504.      }
  505. -    while ((si4700_read_reg(STATUSRSSI) & STATUSRSSI_STC) == 0); /* STC high? */
  506. -
  507. -    si4700_write_clear(CHANNEL, CHANNEL_TUNE); /* Set TUNE low */
  508.  }
  509.  
  510.  static int si4700_tuned(void)
  511. @@ -390,15 +252,14 @@
  512.  static void si4700_set_region(int region)
  513.  {
  514.      const struct si4700_region_data *rd = &si4700_region_data[region];
  515. -    uint16_t bandspacing = SYSCONFIG2_BANDw(rd->band) |
  516. -                           SYSCONFIG2_SPACEw(rd->spacing);
  517. -    uint16_t oldbs = cache[SYSCONFIG2] & (SYSCONFIG2_BAND | SYSCONFIG2_SPACE);
  518. +    uint16_t bandspacing = CHANNEL_BANDw(rd->band) |
  519. +                           CHANNEL_SPACEw(CHANNEL_SPACE_50KHZ);
  520. +    uint16_t oldbs = cache[CHANNEL] & (CHANNEL_BAND | CHANNEL_SPACE);
  521.  
  522. -    si4700_write_masked(SYSCONFIG1,
  523. -                        rd->deemphasis ? SYSCONFIG1_DE : 0,
  524. +    si4700_write_masked(SYSCONFIG1, rd->deemphasis ? SYSCONFIG1_DE : 0,
  525.                          SYSCONFIG1_DE);
  526. -    si4700_write_masked(SYSCONFIG2, bandspacing,
  527. -                        SYSCONFIG2_BAND | SYSCONFIG2_SPACE);
  528. +    si4700_write_masked(CHANNEL, bandspacing, CHANNEL_BAND | CHANNEL_SPACE);
  529. +    si4700_write_cache();
  530.  
  531.      /* Retune if this region change would change the channel number. */
  532.      if (oldbs != bandspacing)
  533. @@ -408,12 +269,12 @@
  534.  /* tuner abstraction layer: set something to the tuner */
  535.  int si4700_set(int setting, int value)
  536.  {
  537. -    switch(setting)
  538. +    switch (setting)
  539.      {
  540.          case RADIO_SLEEP:
  541. -            if (value != 2)
  542. +            if (value != 2) {
  543.                  si4700_sleep(value);
  544. -            /* else actually it's 'pause' */
  545. +            }
  546.              break;
  547.  
  548.          case RADIO_FREQUENCY:
  549. @@ -427,6 +288,9 @@
  550.          case RADIO_MUTE:
  551.              si4700_write_masked(POWERCFG, value ? 0 : POWERCFG_DMUTE,
  552.                                  POWERCFG_DMUTE);
  553. +            si4700_write_masked(SYSCONFIG1, (3 << 9), (3 << 9));
  554. +            si4700_write_masked(SYSCONFIG2, (0xF << 0), (0xF << 0));
  555. +            si4700_write_cache();
  556.              break;
  557.  
  558.          case RADIO_REGION:
  559. @@ -436,6 +300,7 @@
  560.          case RADIO_FORCE_MONO:
  561.              si4700_write_masked(POWERCFG, value ? POWERCFG_MONO : 0,
  562.                                  POWERCFG_MONO);
  563. +            si4700_write_cache();
  564.              break;
  565.  
  566.          default:
  567. @@ -445,6 +310,11 @@
  568.      return 1;
  569.  }
  570.  
  571. +static bool si4700_st(void)
  572. +{
  573. +    return false;
  574. +}
  575. +
  576.  /* tuner abstraction layer: read something from the tuner */
  577.  int si4700_get(int setting)
  578.  {
  579. @@ -470,12 +340,7 @@
  580.  
  581.  void si4700_dbg_info(struct si4700_dbg_info *nfo)
  582.  {
  583. -    memset(nfo->regs, 0, sizeof (nfo->regs));
  584. -
  585. -    if (tuner_powered())
  586. -    {
  587. -        si4700_read(16);
  588. -        memcpy(nfo->regs, cache, sizeof (nfo->regs));
  589. -    }
  590. +    si4700_read(32);
  591. +    memcpy(nfo->regs, cache, sizeof (nfo->regs));
  592.  }
  593.  

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