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#include <statictree.h>
struct device dev_root;
struct device dev_cpus;
struct device dev_apic_0;
struct device dev_domain_0_pci_1_0;
struct device dev_domain_0_pci_f_0;
struct device dev_domain_0_pci_f_1;
struct device dev_domain_0_pci_f_2;
struct device dev_domain_0;
const char *mainboard_vendor = "Artec Group";
const char *mainboard_name = "DBE61";
const u16 mainboard_pci_subsystem_vendor = 0x1022;
const u16 mainboard_pci_subsystem_device = 0x2323;
struct device dev_root = {
	.path =  { .type = DEVICE_PATH_ROOT },
	.on_mainboard = 1,
	.link = {
		[0] = {
			.dev = &dev_root,
			.link = 0,
			.children = &dev_cpus
		},
	},
	.links = 1,
	.bus = &dev_root.link[0],
	.next = &dev_cpus,
	.ops = &default_dev_ops_root,
	.dtsname = "root",
	.enabled = 1
};
struct device dev_cpus = {
	.path = {.type=DEVICE_PATH_CPU},
	.on_mainboard = 1,
	.sibling = &dev_apic_0,
	.links = 0,
	.bus = &dev_root.link[0],
	.next = &dev_apic_0,
	.dtsname = "cpus",
	.enabled = 1
};
struct northbridge_amd_geodelx_apic_config apic_0 = {
}; /*apic_0*/
struct device dev_apic_0 = {
	.path = {.type=DEVICE_PATH_APIC,{.apic={ 0x0 }}},
	.device_configuration = &apic_0,
	.ops = &geodelx_north_apic,
	.on_mainboard = 1,
	.sibling = &dev_domain_0,
	.links = 0,
	.bus = &dev_root.link[0],
	.next = &dev_domain_0_pci_1_0,
	.dtsname = "apic_0",
	.enabled = 1
};
struct northbridge_amd_geodelx_domain_config domain_0 = {
	.geode_video_mb = 0x10,
}; /*domain_0*/
struct device dev_domain_0 = {
	.path = {.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x0 }}},
	.device_configuration = &domain_0,
	.ops = &geodelx_north_domain,
	.on_mainboard = 1,
	.link = {
		[0] = {
			.dev = &dev_domain_0,
			.link = 0,
			.children = &dev_domain_0_pci_1_0
		},
	},
	.links = 1,
	.bus = &dev_root.link[0],
	.dtsname = "domain_0",
	.enabled = 1
};
struct northbridge_amd_geodelx_pci_config domain_0_pci_1_0 = {
}; /*domain_0_pci_1_0*/
struct device dev_domain_0_pci_1_0 = {
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1, 0x0)}}},
	.device_configuration = &domain_0_pci_1_0,
	.ops = &geodelx_north_pci,
	.on_mainboard = 1,
	.sibling = &dev_domain_0_pci_f_0,
	.link = {
		[0] = {
			.dev = &dev_domain_0_pci_1_0,
			.link = 0,
		},
	},
	.links = 1,
	.bus = &dev_domain_0.link[0],
	.next = &dev_domain_0_pci_f_0,
	.dtsname = "domain_0_pci_1_0",
	.enabled = 1
};
struct southbridge_amd_cs5536_dts_config domain_0_pci_f_0 = {
	.lpc_serirq_enable = 0x1002,
	.lpc_serirq_polarity = 0xeffd,
	.lpc_serirq_mode = 0x1,
	.enable_gpio_int_route = 0xd0c0700,
	.enable_ide_nand_flash = 0x2,
	.enable_USBP4_device = 0x0,
	.pph = 0xf5,
	.enable_USBP4_overcurrent = 0x0,
	.com1_enable = 0x0,
	.com1_address = 0x2f8,
	.com1_irq = 0x3,
	.com2_enable = 0x1,
	.com2_address = 0x3f8,
	.com2_irq = 0x4,
	.power_button = 0x0,
	.unwanted_vpci = {
		[0] = 0x0,
	},
}; /*domain_0_pci_f_0*/
struct device dev_domain_0_pci_f_0 = {
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0xf, 0x0)}}},
	.device_configuration = &domain_0_pci_f_0,
	.ops = &cs5536_ops,
	.on_mainboard = 1,
	.sibling = &dev_domain_0_pci_f_1,
	.links = 0,
	.bus = &dev_domain_0.link[0],
	.next = &dev_domain_0_pci_f_1,
	.dtsname = "domain_0_pci_f_0",
	.enabled = 1
};
struct southbridge_amd_cs5536_nand_config domain_0_pci_f_1 = {
}; /*domain_0_pci_f_1*/
struct device dev_domain_0_pci_f_1 = {
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0xf, 0x1)}}},
	.device_configuration = &domain_0_pci_f_1,
	.ops = &cs5536_nand,
	.on_mainboard = 1,
	.sibling = &dev_domain_0_pci_f_2,
	.links = 0,
	.bus = &dev_domain_0.link[0],
	.next = &dev_domain_0_pci_f_2,
	.dtsname = "domain_0_pci_f_1",
	.enabled = 1
};
struct southbridge_amd_cs5536_ide_config domain_0_pci_f_2 = {
	.enable_ide = 0x0,
}; /*domain_0_pci_f_2*/
struct device dev_domain_0_pci_f_2 = {
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0xf, 0x2)}}},
	.device_configuration = &domain_0_pci_f_2,
	.ops = &cs5536_ide,
	.on_mainboard = 1,
	.links = 0,
	.bus = &dev_domain_0.link[0],
	.next = &dev_domain_0,
	.dtsname = "domain_0_pci_f_2",
	.enabled = 0
};
struct device_operations *all_device_operations[] = {
	&geodelx_north_apic,
	&geodelx_north_domain,
	&geodelx_north_pci,
	&cs5536_ops,
	&cs5536_nand,
	&cs5536_ide,
	0
};