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Untitled
Tuesday, January 6th, 2009 at 12:01:07pm MST 

  1. #include <statictree.h>
  2. struct device dev_root;
  3. struct device dev_cpus;
  4. struct device dev_apic_0;
  5. struct device dev_domain_0_pci_1_0;
  6. struct device dev_domain_0_pci_f_0;
  7. struct device dev_domain_0_pci_f_1;
  8. struct device dev_domain_0_pci_f_2;
  9. struct device dev_domain_0;
  10. const char *mainboard_vendor = "Artec Group";
  11. const char *mainboard_name = "DBE61";
  12. const u16 mainboard_pci_subsystem_vendor = 0x1022;
  13. const u16 mainboard_pci_subsystem_device = 0x2323;
  14. struct device dev_root = {
  15.         .path =  { .type = DEVICE_PATH_ROOT },
  16.         .on_mainboard = 1,
  17.         .link = {
  18.                 [0] = {
  19.                         .dev = &dev_root,
  20.                         .link = 0,
  21.                         .children = &dev_cpus
  22.                 },
  23.         },
  24.         .links = 1,
  25.         .bus = &dev_root.link[0],
  26.         .next = &dev_cpus,
  27.         .ops = &default_dev_ops_root,
  28.         .dtsname = "root",
  29.         .enabled = 1
  30. };
  31. struct device dev_cpus = {
  32.         .path = {.type=DEVICE_PATH_CPU},
  33.         .on_mainboard = 1,
  34.         .sibling = &dev_apic_0,
  35.         .links = 0,
  36.         .bus = &dev_root.link[0],
  37.         .next = &dev_apic_0,
  38.         .dtsname = "cpus",
  39.         .enabled = 1
  40. };
  41. struct northbridge_amd_geodelx_apic_config apic_0 = {
  42. }; /*apic_0*/
  43. struct device dev_apic_0 = {
  44.         .path = {.type=DEVICE_PATH_APIC,{.apic={ 0x0 }}},
  45.         .device_configuration = &apic_0,
  46.         .ops = &geodelx_north_apic,
  47.         .on_mainboard = 1,
  48.         .sibling = &dev_domain_0,
  49.         .links = 0,
  50.         .bus = &dev_root.link[0],
  51.         .next = &dev_domain_0_pci_1_0,
  52.         .dtsname = "apic_0",
  53.         .enabled = 1
  54. };
  55. struct northbridge_amd_geodelx_domain_config domain_0 = {
  56.         .geode_video_mb = 0x10,
  57. }; /*domain_0*/
  58. struct device dev_domain_0 = {
  59.         .path = {.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x0 }}},
  60.         .device_configuration = &domain_0,
  61.         .ops = &geodelx_north_domain,
  62.         .on_mainboard = 1,
  63.         .link = {
  64.                 [0] = {
  65.                         .dev = &dev_domain_0,
  66.                         .link = 0,
  67.                         .children = &dev_domain_0_pci_1_0
  68.                 },
  69.         },
  70.         .links = 1,
  71.         .bus = &dev_root.link[0],
  72.         .dtsname = "domain_0",
  73.         .enabled = 1
  74. };
  75. struct northbridge_amd_geodelx_pci_config domain_0_pci_1_0 = {
  76. }; /*domain_0_pci_1_0*/
  77. struct device dev_domain_0_pci_1_0 = {
  78.         .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1, 0x0)}}},
  79.         .device_configuration = &domain_0_pci_1_0,
  80.         .ops = &geodelx_north_pci,
  81.         .on_mainboard = 1,
  82.         .sibling = &dev_domain_0_pci_f_0,
  83.         .link = {
  84.                 [0] = {
  85.                         .dev = &dev_domain_0_pci_1_0,
  86.                         .link = 0,
  87.                 },
  88.         },
  89.         .links = 1,
  90.         .bus = &dev_domain_0.link[0],
  91.         .next = &dev_domain_0_pci_f_0,
  92.         .dtsname = "domain_0_pci_1_0",
  93.         .enabled = 1
  94. };
  95. struct southbridge_amd_cs5536_dts_config domain_0_pci_f_0 = {
  96.         .lpc_serirq_enable = 0x1002,
  97.         .lpc_serirq_polarity = 0xeffd,
  98.         .lpc_serirq_mode = 0x1,
  99.         .enable_gpio_int_route = 0xd0c0700,
  100.         .enable_ide_nand_flash = 0x2,
  101.         .enable_USBP4_device = 0x0,
  102.         .pph = 0xf5,
  103.         .enable_USBP4_overcurrent = 0x0,
  104.         .com1_enable = 0x0,
  105.         .com1_address = 0x2f8,
  106.         .com1_irq = 0x3,
  107.         .com2_enable = 0x1,
  108.         .com2_address = 0x3f8,
  109.         .com2_irq = 0x4,
  110.         .power_button = 0x0,
  111.         .unwanted_vpci = {
  112.                 [0] = 0x0,
  113.         },
  114. }; /*domain_0_pci_f_0*/
  115. struct device dev_domain_0_pci_f_0 = {
  116.         .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0xf, 0x0)}}},
  117.         .device_configuration = &domain_0_pci_f_0,
  118.         .ops = &cs5536_ops,
  119.         .on_mainboard = 1,
  120.         .sibling = &dev_domain_0_pci_f_1,
  121.         .links = 0,
  122.         .bus = &dev_domain_0.link[0],
  123.         .next = &dev_domain_0_pci_f_1,
  124.         .dtsname = "domain_0_pci_f_0",
  125.         .enabled = 1
  126. };
  127. struct southbridge_amd_cs5536_nand_config domain_0_pci_f_1 = {
  128. }; /*domain_0_pci_f_1*/
  129. struct device dev_domain_0_pci_f_1 = {
  130.         .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0xf, 0x1)}}},
  131.         .device_configuration = &domain_0_pci_f_1,
  132.         .ops = &cs5536_nand,
  133.         .on_mainboard = 1,
  134.         .sibling = &dev_domain_0_pci_f_2,
  135.         .links = 0,
  136.         .bus = &dev_domain_0.link[0],
  137.         .next = &dev_domain_0_pci_f_2,
  138.         .dtsname = "domain_0_pci_f_1",
  139.         .enabled = 1
  140. };
  141. struct southbridge_amd_cs5536_ide_config domain_0_pci_f_2 = {
  142.         .enable_ide = 0x0,
  143. }; /*domain_0_pci_f_2*/
  144. struct device dev_domain_0_pci_f_2 = {
  145.         .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0xf, 0x2)}}},
  146.         .device_configuration = &domain_0_pci_f_2,
  147.         .ops = &cs5536_ide,
  148.         .on_mainboard = 1,
  149.         .links = 0,
  150.         .bus = &dev_domain_0.link[0],
  151.         .next = &dev_domain_0,
  152.         .dtsname = "domain_0_pci_f_2",
  153.         .enabled = 0
  154. };
  155. struct device_operations *all_device_operations[] = {
  156.         &geodelx_north_apic,
  157.         &geodelx_north_domain,
  158.         &geodelx_north_pci,
  159.         &cs5536_ops,
  160.         &cs5536_nand,
  161.         &cs5536_ide,
  162.         0
  163. };

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